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KR-20260065314-A - SEMICONDUCTOR DEVICE INCLUDING BONDING PADS AND Method for measuring contact resistance of bonding pads

KR20260065314AKR 20260065314 AKR20260065314 AKR 20260065314AKR-20260065314-A

Abstract

According to embodiments of the present disclosure, a semiconductor device comprises: a memory chip comprising a cell bonding pad disposed in a cell region and upper test pads disposed outside the cell region and comprising a first upper test pad, a second upper test pad, and a third upper test pad; a circuit chip comprising a peri-bonding pad disposed in the cell region and bonded to the cell bonding pad and lower test pads disposed outside the cell region and comprising a first lower test pad, a second lower test pad, and a third lower test pad; and test patterns disposed outside the cell region, each comprising at least a portion of the upper test pads and the lower test pads, wherein the test patterns include a first test pattern in which a first upper test pad, a first upper test contact connected to each of the first upper test pads, and a first upper conductive layer connecting the first upper test contacts connected to different first upper test pads are sequentially connected, a second lower test pad, a second lower test contact connected to each of the second lower test pads, and the second lower test contacts connected to different second lower test pads. It may include a second test pattern in which a connecting second lower conductive layer is connected in sequence, a third upper conductive layer, a third lower conductive layer, and a third test pattern including a third upper test contact, a third upper test pad, a third lower test pad, and a third lower test contact connecting between the third upper and lower conductive layers.

Inventors

  • 장헌용

Assignees

  • 에스케이하이닉스 주식회사

Dates

Publication Date
20260508
Application Date
20241101

Claims (18)

  1. A memory chip comprising a cell bonding pad disposed in a cell region and upper test pads disposed outside the cell region, including a first upper test pad, a second upper test pad, and a third upper test pad; A circuit chip comprising a peri-bonding pad disposed in the cell region and bonded to the cell bonding pad, and lower test pads disposed outside the cell region and including a first lower test pad, a second lower test pad, and a third lower test pad; and Test patterns disposed outside the cell area, each comprising at least some of the upper test pads and the lower test pads, and The above test patterns are, A first test pattern in which the first upper test pad, a first upper test contact connected to each of the first upper test pads, and a first upper conductive layer connecting the first upper test contacts connected to different first upper test pads are connected in sequence; A second test pattern in which the second lower test pad, a second lower test contact connected to each of the second lower test pads, and a second lower conductive layer connecting the second lower test contacts connected to each of the different second lower test pads are connected in sequence; and A third test pattern comprising a third upper conductive layer, a third lower conductive layer, and a third upper test contact, a third upper test pad, a third lower test pad, and a third lower test contact connecting the third upper and lower conductive layers; A semiconductor device including
  2. In paragraph 1, It further includes a pair of probing pads connected to each of the first, second, or third test patterns, and The above probing pads include a first probing input pad and a first probing output pad connected to the first test pattern at different locations, a second probing input pad and a second probing output pad connected to the second test pattern at different locations, and a third probing input pad and a third probing output pad connected to the third test pattern at different locations. A semiconductor device in which voltages of different magnitudes are applied to each of the first probing input pad and the first probing output pad, the second probing input pad and the second probing output pad, or the third probing input pad and the third probing output pad, and the resistance between the first probing input pad and the first probing output pad, the second probing input pad and the second probing output pad, or the third probing input pad and the third probing output pad is measured from the current value flowing between the first probing input pad and the first probing output pad, the second probing input pad and the second probing output pad, or the third probing input pad and the third probing output pad.
  3. In paragraph 2, Voltages of different magnitudes are applied to the first probing input and output pads connected to the first test pattern, and a first resistance between the first upper test pad and the first upper test contact is measured from the current value flowing between the first probing input and output pads, and Voltages of different magnitudes are applied to the second probing input and output pads connected to the second test pattern, and the second resistance between the second lower test pad and the second lower test contact is measured from the current value flowing between the first probing input and output pads, and Voltages of different magnitudes are applied to the third probing input and output pads connected to the third test pattern, and the third resistance between the third upper test contact and the third lower test contact is measured from the current value flowing between the third probing input and output pads, and A semiconductor device in which the contact resistance between the cell bonding pad and the peri-bonding pad is measured by subtracting the first and second resistances from the third resistance.
  4. In paragraph 1, The above first test pattern is a semiconductor device further comprising a first lower test pad bonded to each of the first upper test pads.
  5. In paragraph 1, The above second test pattern is a semiconductor device further comprising a second upper test pad bonded to each of the above second lower test pads.
  6. In paragraph 1, A semiconductor device in which the third upper test pad included in the above third test pattern overlaps with two or more of the above third lower test pads.
  7. In paragraph 6, Voltages of different magnitudes are applied to the second probing input and output pads connected to the second test pattern, and the second resistance between the second lower test pad and the second lower test contact is measured from the current value flowing between the second probing input and output pads. Voltages of different magnitudes are applied to the third probing input and output pads connected to the third test pattern, and a fourth resistance between the third upper test pad and the third lower test contact is measured from the current value flowing between the third probing input and output pads, and A semiconductor device in which the contact resistance between the cell bonding pad and the peri bonding pad is measured by subtracting the second resistance from the fourth resistance.
  8. In paragraph 1, The first to third upper test pads are semiconductor devices disposed on the same layer as the cell bonding pad.
  9. In paragraph 1, The memory chip further includes a peripheral region around the cell region, and The first, second, and third test patterns are semiconductor devices placed in the ferri region.
  10. In paragraph 1, The memory chip further includes a chip region comprising the cell region and a peripheral region surrounding the cell region, and The first, second, and third test patterns are a semiconductor device disposed in a scribe lane area continuous with the chip area.
  11. A memory chip comprising cell bonding pads disposed in a cell area and upper test pads disposed outside the cell area; A circuit chip comprising a peri-bonding pad disposed in the cell region and bonded to the cell bonding pad, and lower test pads disposed outside the cell region; and Test patterns disposed outside the cell area and including at least some of the upper test pads and the lower test pads, At least one of the above test patterns is, A semiconductor device comprising some of the upper test pads and some of the lower test pads, wherein each of the test pads of the portion is bonded to two of the lower test pads of the portion, and each of the lower test pads of the portion is bonded to two of the test pads of the portion.
  12. In Paragraph 11, It further includes a pair of probing pads connected to at least one of the above test patterns, The above probing pads include a probing input pad and a probing output pad connected to at least one test pattern at different locations, A semiconductor device in which voltages of different magnitudes are applied to the probing input and output pads, and the resistance between the probing input and output pads is measured from the current value flowing between the probing input and output pads.
  13. In Paragraph 12, A semiconductor device in which voltages of different magnitudes are applied to the probing input and output pads connected to at least one of the above test patterns, and the contact resistance between the upper test pad and the lower test pad is measured by measuring the resistance between the probing input and output pads from the current value flowing between the probing input and output pads.
  14. In Paragraph 11, The memory chip further includes a peripheral region around the cell region, and The above at least one test pattern is a semiconductor device disposed in the above-mentioned periphery.
  15. A contact resistance measuring method for determining the bonding strength between a cell bonding pad and a peri-bonding pad bonded to each other using at least some of upper test pads including a first upper test pad, a second upper test pad, and a third upper test pad, and lower test pads including a first lower test pad, a second upper test pad, and a third lower test pad, wherein A step of measuring a first resistance between a first upper test pad and a first upper test contact connected to the first upper test pad; A step of measuring a second resistance between a second lower test pad and a second lower test contact connected to the second lower test pad; A step of measuring a third resistance between the third upper test contact and the third lower test contact in a test pattern in which the third upper test contact, the third upper test pad, the third lower test pad, and the third lower test contact are connected in sequence; and A step of measuring the contact resistance between the cell and the peri-bonding pad by subtracting the first and second resistances from the third resistance, and evaluating the bonding strength between the cell and the peri-bonding pad based thereon; A contact resistance measurement method including
  16. In paragraph 15, The step of measuring the first resistance above is, A step of connecting a pair of probing pads to a first test pattern in which the first upper test pad, the first upper test contact, and a first upper conductive layer connecting the first upper test contacts each connected to the different first upper test pads are connected in sequence; A step of applying different voltages to each of the above pair of probing pads; A contact resistance measurement method including
  17. In paragraph 15, The step of measuring the second resistance above is, A step of connecting a pair of probing pads to a second test pattern in which the second lower test pad, the second lower test contact, and a second lower conductive layer connecting the second lower test contacts each connected to the different second lower test pads are connected in sequence; A step of applying different voltages to each of the above pair of probing pads; A contact resistance measurement method including
  18. In paragraph 15, In the step of measuring the third resistance above, A contact resistance measurement method in which one of the above-mentioned third upper test pads overlaps with at least two of the above-mentioned third lower test pads.

Description

Semiconductor device including bonding pads and method for measuring contact resistance of bonding pads The embodiments of the present disclosure relate to a semiconductor device comprising bonding pads and a method for measuring the contact resistance of the bonding pads. Due to characteristics such as miniaturization, multifunctionality, and/or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. As the electronics industry advances, semiconductor devices are becoming increasingly highly integrated. To achieve this high integration, a technology is being utilized in which the components and circuits included in the semiconductor device are formed on two wafers, and then the two wafers are bonded vertically using wafer bonding technology. FIG. 1 is a drawing showing an example of a planar structure of a semiconductor device according to embodiments of the present disclosure. FIG. 2 is a diagram briefly illustrating an example of a cross-sectional structure of a semiconductor device according to embodiments of the present disclosure. FIGS. 3 to 9 are drawings illustrating examples of cross-sectional structures of a semiconductor device according to embodiments of the present disclosure. FIG. 10 is a drawing showing another example of a planar structure of a semiconductor device according to embodiments of the present disclosure. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the attached drawings, two directions parallel to the upper surface of the substrate will be defined as the first direction (FD) and the second direction (SD), respectively, and a direction protruding perpendicularly from the upper surface of the substrate will be defined as the third direction (VD). The first direction (FD) and the second direction (SD) may be substantially perpendicular to each other. The third direction (VD) is a direction perpendicular to the first direction (FD) and the second direction (SD). In the following specification, 'perpendicular' or 'perpendicular direction' will be used with substantially the same meaning as the third direction (VD). In the drawings, directions indicated by arrows and opposite directions represent the same direction. FIG. 1 is a drawing showing an example of a planar structure of a semiconductor device according to embodiments of the present disclosure. Referring to FIG. 1, the semiconductor device includes a chip region (CHR). The semiconductor device may include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), Flash Memory, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase-change Random Access Memory), FRAM (Ferroelectric Random Access Memory), RRAM (Resistive Random Access Memory), or a combination thereof. In one embodiment, the semiconductor device may be a memory device including a NAND flash memory cell. Below, the case where the semiconductor device is a memory device including a NAND flash memory cell is described as an example. The chip region (CHR) includes a cell region (CR) and a periphery region (PR). The cell region (CR) is an area where a memory cell array is placed. The periphery region (PR) is placed around the cell region (CR). The periphery region (PR) is an area where various circuits connected to the memory cell array are placed. In one embodiment, the chip region (CHR) may include four cell regions (CR). Each cell region (CR) may be surrounded by a periphery region (PR). In one embodiment, test patterns (101, 102, 103) may be placed in a ferri region (PR). Test patterns (101, 102, 103) include a first test pattern (101), a second test pattern (102), and a third test pattern (103). Test patterns (101, 102, 103) may include monitoring patterns or various test patterns for monitoring whether a semiconductor device is defective. In an embodiment according to the present disclosure, test patterns (101, 102, 103) may be patterns for measuring resistance between metal layers included in a semiconductor device. Each of the test patterns (101, 102, 103) may be placed at any location within the ferri region (PR). In FIG. 1, test patterns (101, 102, 103) are shown placed between different cell regions (CR), but the locations where test patterns (101, 102, 103) are placed are not limited thereto. FIG. 2 is a diagram briefly illustrating an example of a cross-sectional structure of a semiconductor device according to embodiments of the present disclosure. Referring to FIG. 2, the semiconductor device includes a memory chip (C1), a circuit chip (C2), and test patterns (101, 102, 103). The memory chip (C1) and the circuit chip (C2) may each be semiconductor chips manufactured on different wafers. In the cell region (CR), the memory chip (C1) may include a memory cell array (210) and a cell bonding pad (201). The circuit chip (C2) may include a logic circuit (220) and a peribonding pad (202). The logic c