KR-20260065331-A - SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

KR20260065331AKR 20260065331 AKR20260065331 AKR 20260065331AKR-20260065331-A

Abstract

The present invention proposes a semiconductor device and a method for manufacturing the same. The semiconductor device of the present invention comprises a semiconductor substrate of a first conductivity type, an epitaxial layer of a first conductivity type on the semiconductor substrate, and a drift layer of a first conductivity type on the epitaxial layer. The drift layer located in a junction termination region of the semiconductor device is etched to a predetermined thickness, and a field oxide film is formed in the etched region to eliminate the step difference between the junction termination region and an adjacent active region. When the field oxide film is formed, a region in which a dopant has been injected in advance is formed as a doping region.

Inventors

조영서
임지용
김기환

Assignees

매그나칩 반도체 유한회사

Dates

Publication Date: 20260508
Application Date: 20241101

Claims (20)

It includes an active region and a junction termination region, and each of the said regions is, Drain electrode; A first epitaxial layer of a first conductivity type formed on the drain electrode; A second epitaxial layer of the first conductivity type formed on the first epitaxial layer of the first conductivity type; A first junction termination region formed by etching a portion of a second epitaxial layer of a first conductivity type located in the junction termination region, and a second junction termination region that is not etched; A field oxidation film formed in a part of the first junction termination region; and A semiconductor device characterized by including a second conductivity type doping region formed by extending from the lower part of the field oxide film to the second junction termination region.
In paragraph 1, The doping region of the second challenge type mentioned above is, A second conductivity type low-concentration doping region formed in the first junction termination region; A semiconductor device characterized by including a second high-concentration doping region of a second conductivity type that is extended from a part of the first junction termination region to the second junction termination region.
In paragraph 2, A semiconductor device characterized in that the thickness of the high-concentration doping region of the second conductivity type is thicker than the thickness of the low-concentration doping region of the second conductivity type.
In Article 1, A semiconductor device characterized in that the surface of the field oxide film and the surface of the second epitaxial layer of the first conductivity type existing in the second junction termination region are located on the same plane.
In Article 1, A second conductive body region formed between the trench gates of the above active region; A semiconductor device characterized in that the body region of the second conductivity type and the doping region of the second conductivity type are connected to each other.
In paragraph 1, A semiconductor device characterized by including a second conductivity type layer formed between the drain electrode and a first conductivity type epitaxial layer.
In Article 1, The above junction termination area is, A junction termination etching region exists between the field oxide film and the second junction termination region, and Field plate insulating film formed on the inner and outer upper surfaces of the junction termination etching area; A field plate formed on the insulating film of the field plate above; An interlayer insulating film formed on the field plate above; and A semiconductor device characterized by including a source electrode and a gate electrode formed on the interlayer insulating film.
It includes an active region and a junction termination region, and each of the said regions is, Drain electrode; A first epitaxial layer of a first conductivity type formed on the drain electrode; A second epitaxial layer of the first conductivity type formed on the first epitaxial layer of the first conductivity type; A first junction termination region formed by etching a portion of the second epitaxial layer of the first conductivity type located in the junction termination region, and a second junction termination region that is not etched; A field oxide film formed in a portion of the first junction termination region; and A semiconductor device characterized by having a second conductivity type doping region of different thicknesses formed in the first junction termination region and the second junction termination region.
In paragraph 8, A second conductive body region formed between the trench gates of the above active region; A semiconductor device characterized by the body region of the second conductivity type and the doping region of the second conductivity type being connected to each other.
In paragraph 8, The doping region of the second conductivity type with a different thickness above is, A second low-concentration doping region of the second conductivity type formed in the first junction termination region; A semiconductor device characterized by including: a second conductivity type high-concentration doping region formed by extending from a part of the first junction termination to a second junction termination region and having a higher concentration than the second conductivity type low-concentration doping region.
In Paragraph 10, A semiconductor device characterized in that the thickness of the high-concentration doping region of the second conductivity type is formed to be thicker than the thickness of the low-concentration doping region of the second conductivity type.
In Paragraph 10, A semiconductor device characterized in that the concentration of the low-concentration doping region of the second conductivity type gradually decreases as it moves toward the edge direction of the first junction termination region.
In Paragraph 10, A source electrode electrically in contact with the high-concentration doping region of the second conductivity type above; A field plate formed on a portion of the high-concentration doping region of the second conductivity type and the low-concentration doping region of the second conductivity type; A semiconductor device characterized by including a gate electrode that is electrically in contact with the field plate.
In Paragraph 10, A semiconductor device characterized by including a second conductivity type layer formed between the drain electrode and a first conductivity type epitaxial layer.
It includes an active region and a junction termination region, A step of forming a first epitaxial layer of a first conductivity type on a semiconductor substrate of a first conductivity type; A step of forming a second epitaxial layer of the first conductivity type on the first epitaxial layer of the first conductivity type; A step of etching a portion of the upper surface of the second epitaxial layer of the first conductivity type located in the junction termination region; A step of forming a first ion implantation region by first implanting ions of a second conductivity type into an unetched junction termination region and an etched junction termination region after the above etching step; A step of forming a second ion implantation region by secondarily implanting ions of a second conductivity type into a portion of an unetched junction termination region and an etched junction termination region after the first ion implantation; and A method for manufacturing a semiconductor device characterized by including the step of forming a field oxide film on a portion of the junction termination region etched through a thermal oxidation process.
In paragraph 15, A method for manufacturing a semiconductor device characterized by the fact that the ions injected during the formation of the field oxide film diffuse into each other to form a doping region of a second conductivity type.
In paragraph 15, A method for manufacturing a semiconductor device, characterized in that the mask pattern disposed when forming the first ion implantation region is formed such that the spacing between the mask patterns becomes progressively narrower as it approaches the edge region.
In Paragraph 14, A method for manufacturing a semiconductor device characterized by the fact that the ion concentration of the second conductivity type during the first injection and the second injection is the same.
In paragraph 15, A step of forming a junction termination etching region after the above field oxide film formation step; A step of forming a field plate insulating film within the junction termination etching region; A step of forming a field plate on the field plate insulating film above; A step of forming an interlayer insulating film on the field plate; and A method for manufacturing a semiconductor device, further comprising the step of etching a portion of the interlayer insulating film to form a gate electrode in contact with the field plate and a source electrode in contact with a doping region of the second conductivity type on the etched region.
In paragraph 15, A step of performing a polishing process on the lower surface of the first conductivity type semiconductor substrate; A step of forming a second conductivity type layer by performing a second conductivity type ion implantation process after the above polishing process; and A method for manufacturing a semiconductor device characterized by further including the step of forming a drain electrode on the lower surface of the second conductivity type layer.

Description

Super Junction Semiconductor Device and Method of Manufacturing the Same The present invention relates to a semiconductor device capable of securing a more stable internal pressure than conventional devices and a method for manufacturing the same. Power semiconductor devices such as MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are primarily used as semiconductor switching devices in power electronics applications. Among these power semiconductor devices, IGBTs can be classified into a horizontal structure in which source (or emitter), gate (or base), and drain (or collector) electrodes are all formed on the upper surface of a semiconductor substrate, or a vertical structure in which source and gate electrodes are formed on the upper surface of the semiconductor substrate and a drain electrode is formed on the back surface. For dual IGBT devices, it is essential to reduce the electric field peaks generated at the substrate surface of the junction termination. The maximum electric field peak typically occurs within an equipotential ring located in the junction termination region; however, this region becomes very weak under extreme conditions of high current and high voltage, leading to avalanche breakdown under reverse voltage bias due to high leakage current density. To prevent this, methods to reduce the electric field have been proposed, such as adopting a P-ring structure that forms multiple P-type conductivity types or increasing the junction termination region. A P-ring structure forming multiple P-type conduction types can reduce the electric field beyond a certain level, but there are limitations in the case of high-voltage devices, and increasing the junction termination area has the disadvantage of increasing the device size. Such IGBT semiconductor devices must be able to disperse the electric field generated when reverse bias is applied due to the device characteristics, thereby lowering the electric field peak value and securing a stable breakdown voltage. This is because it is particularly related to the breakdown voltage of the semiconductor device. Therefore, various methods to improve the structure of semiconductor devices have been proposed to enhance voltage withstand performance. FIG. 1 is a cross-sectional structural diagram for explaining a semiconductor device according to the prior art. Figure 2a is the doping concentration profile of the semiconductor device of Figure 1, and Figure 2b is the electric field profile of the semiconductor device of Figure 1. FIG. 3 is a cross-sectional structural diagram illustrating another semiconductor device of a PBR structure according to the prior art. Figure 4a is the doping concentration profile of the semiconductor device of Figure 3, and Figure 4b is the electric field profile of the semiconductor device of Figure 3. FIGS. 5 to 10 are process drawings illustrating a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 11 is a configuration diagram of a semiconductor device according to the present embodiment. FIGS. 12 to 14 are drawings comparing the Impact Ionization Profile, Electric Field, and Potential of the semiconductor device of the present invention and the prior art, respectively. FIG. 15 is a flowchart of the manufacturing process of a semiconductor device according to the present embodiment. The present invention is capable of various modifications and may have various embodiments, and specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the invention to specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. In describing the invention, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may obscure the essence of the invention. Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. The terms used in this invention are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Spatially relative terms such as "below," "beneath," "lower," and "above" or "upper" may be used to facilitate the descript