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KR-20260065351-A - SEMICONDUCTOR DEVICE

KR20260065351AKR 20260065351 AKR20260065351 AKR 20260065351AKR-20260065351-A

Abstract

According to one embodiment of the present disclosure, the present disclosure may provide a semiconductor device comprising a substrate, a plurality of transistor structures disposed on the substrate and spaced apart from each other in a first direction parallel to the surface of the substrate, each comprising a lower active pattern and an upper active pattern spaced apart from the lower active pattern in a second direction intersecting the first direction, a gate cutting film disposed between the plurality of transistor structures, a first layer surrounding at least a portion of each lower active pattern and a second layer disposed on the first layer, wherein the plurality of transistor structures each comprise a first work function film surrounding at least a portion of the lower active pattern and a second work function film surrounding at least a portion of the upper active pattern and extending in a first direction, and the gate cutting film penetrates the second work function film so as to cut the second work function film along the second direction.

Inventors

  • 문병호
  • 김민우
  • 황동훈
  • 김성광
  • 김현수
  • 이원창
  • 전재호

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260508
Application Date
20241101

Claims (10)

  1. substrate, A plurality of transistor structures are arranged on the substrate and spaced apart from each other in a first direction parallel to the surface of the substrate, each comprising a lower active pattern and an upper active pattern spaced apart from the lower active pattern in a second direction intersecting the first direction. A gate cutting film disposed between the plurality of transistor structures above, A first layer surrounding at least a portion of each of the above-mentioned lower active patterns and It includes a second layer disposed on the first layer, and Each of the above plurality of transistor structures includes a first work function film surrounding at least a portion of the lower active pattern and a second work function film surrounding at least a portion of the upper active pattern and extending in the first direction. The gate cutting film penetrates the second work function film so that the second work function film is cut along the second direction. Semiconductor device.
  2. In Article 1, A portion of the first work function film is cut and arranged along the second direction between the plurality of transistor structures, Semiconductor device.
  3. In Article 1, It further includes a separating insulating film disposed between the lower active pattern and the upper active pattern, The above-mentioned separating insulating film is in contact with the above-mentioned second work function film, Semiconductor device.
  4. In Article 1, At least some of the above plurality of transistor structures are, A first transistor structure comprising a region in which the first work function film and the second work function film are in contact, Semiconductor device.
  5. In Article 4, In the first transistor structure above, The surface area of the region where the second work function film and the second layer are in contact is larger than the surface area of the region where the first work function film and the second work function film are in contact. Semiconductor device.
  6. In Article 1, At least some of the above plurality of transistor structures are, With respect to the second direction, the upper surface of the first work function film includes a second transistor structure adjacent to the substrate than the lower surface of the second work function film. Semiconductor device.
  7. In Article 6, The above second transistor structure is, It further includes a separating insulating film disposed between the lower active pattern and the upper active pattern, The ratio ( T1 / T2 ) of the length ( T1 ) between the upper surface of the first work function film and the lower surface of the second work function film with respect to the second direction and the length ( T2 ) of the separating insulating film is 0.5 or less, Semiconductor device.
  8. In Article 1, The first layer and the second layer each independently comprise an insulating material, and A portion of the first layer is arranged continuously with respect to the first direction between the plurality of transistor structures, Semiconductor device.
  9. In Article 1, The first layer comprises a conductive material, and the second layer comprises an insulating material, and A portion of the first layer is cut and arranged along the second direction between the plurality of transistor structures, Semiconductor device.
  10. substrate, A plurality of transistor structures comprising: a lower active pattern disposed on the substrate and spaced apart from each other in a first direction parallel to the surface of the substrate, each comprising a plurality of spaced sheets; an upper active pattern spaced apart from the lower active pattern in a second direction intersecting the first direction and comprising a plurality of spaced sheets; and a separating insulating film disposed between the lower active pattern and the upper active pattern. A gate cutting film disposed between the plurality of transistor structures above, A first layer surrounding at least a portion of each of the above-mentioned lower active patterns and It includes a second layer disposed on the first layer, and Each of the above plurality of transistor structures includes a first work function film surrounding at least a portion of the lower active pattern and a second work function film surrounding at least a portion of the upper active pattern and extending in the first direction. The gate cutting film penetrates the second work function film in the second direction so that the second work function film is cut with respect to the first direction. Semiconductor device.

Description

Semiconductor Device The present disclosure relates to a semiconductor device. Fin field-effect transistors (FinFETs) and nanosheet field-effect transistors have been introduced as technologies for high-density devices and high-performance integrated circuits. A FinFET comprises a channel layer with at least three sides surrounded by a gate structure and has one or more vertical fin structures arranged horizontally. Nanosheet field-effect transistors are known, for example, as gate-all-around (GAA) transistors or multi-bridge channel (MBC) transistor products, and comprise one or more nanosheet channel layers stacked vertically on a substrate and a gate structure surrounding the front of each nanosheet channel layer. Meanwhile, to increase device density, a 3D stacked field-effect transistor (3DSFET) in which a bottom nanosheet field-effect transistor and a top nanosheet field-effect transistor are stacked has been proposed. Recently, due to the downscaling of semiconductor devices, the size of standard cells included in integrated circuits is decreasing, and in the case of devices including cross-coupled structures, design rules must not be violated to implement standard cells of reduced size. The drawings shown in this disclosure are according to embodiments, and the ratios of the width, height, or height (or thickness) of each component are intended to explain this disclosure in detail and may differ from the actual. Additionally, in the coordinate system shown in the drawings, each axis may be perpendicular to the others, the direction indicated by the arrow may be the + direction, and the direction exactly opposite to the direction indicated by the arrow (a direction rotated 180 degrees) may be the - direction. FIG. 1 is an exemplary layout drawing of a semiconductor device according to one embodiment of the present disclosure. FIG. 2 is an exemplary drawing showing a cross-section cut along I-I' of FIG. 1. Figure 3 is an enlarged view of section P of Figure 2. Figure 4 is another exemplary drawing showing a cross-section cut along I-I' of Figure 1. Figure 5 is an enlarged view of section Q of Figure 4. Figure 6 is an enlarged view of the R portion of Figure 4. FIG. 7 is an exemplary drawing showing a first transistor structure including a common gate structure and a second transistor structure including a split gate structure with the dummy gate structure surrounding the active patterns removed. Figure 8 is an exemplary diagram showing the formation of a sacrificial membrane between upper active patterns. Figure 9 is an exemplary diagram showing the formation of a gate dielectric film. Figure 10 is an exemplary diagram showing the formation of a sacrificial membrane between upper active patterns. FIG. 11 is an exemplary drawing showing the formation of a first work function film. FIG. 12 is an exemplary drawing illustrating a method for manufacturing a semiconductor device according to a first embodiment, showing the appearance before a mask is formed while leaving a portion between a first transistor structure and a second transistor structure, and before a portion of a first work function film is cut. FIG. 13 is an exemplary drawing illustrating a method for manufacturing a semiconductor device according to a first embodiment, in which a portion of a first work function film disposed between a first transistor structure and a second transistor structure is cut to form a recess, and a first layer containing an insulating material is deposited. FIG. 14 is an exemplary drawing illustrating a method for manufacturing a semiconductor device according to a first embodiment, showing a polymer layer formed after removing a first layer formed on a second transistor structure. FIG. 15 is an exemplary drawing illustrating a method for manufacturing a semiconductor device according to a first embodiment, showing a portion of a first work function film formed on a second transistor structure removed. FIG. 16 is an exemplary drawing illustrating a method for manufacturing a semiconductor device according to a first embodiment, showing the appearance of removing a first layer formed on a first transistor structure after removing a polymer layer. FIG. 17 is an exemplary drawing illustrating a method for manufacturing a semiconductor device according to a first embodiment, showing a first layer containing an insulating material that has been deposited again. FIG. 18 is an exemplary drawing illustrating a method for manufacturing a semiconductor device according to a first embodiment, showing a polymer layer formed and then a portion of the first layer formed on a first transistor structure and a second transistor structure removed. FIG. 19 is an exemplary drawing illustrating a method for manufacturing a semiconductor device according to a first embodiment, showing a second layer containing an insulating material deposited after removing a polymer layer. FIG. 20 is an exemplary drawing for explaining a method of man