KR-20260065394-A - Nonvolatile memory devices using ion redistribution and methods of manufacturing the same and electronic apparatuses including nonvolatile memory device

Abstract

A non-volatile memory device using ion redistribution, a method for manufacturing the same, and an electronic device including the non-volatile memory device are disclosed. A memory device according to one embodiment includes a first semiconductor layer including a channel and a gate stack provided on the channel of the first semiconductor layer. The gate stack includes an electrolyte layer containing mobile ions whose distribution state changes according to an applied voltage, and first and second barrier layers disposed facing each other with the electrolyte layer in between.

Inventors

• 김선호
• 이민현
• 박가람

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20241101

Claims (20)

1. A first semiconductor layer including a channel; and A gate stack provided on the channel of the first semiconductor layer; comprising The above gate stack is, An electrolyte layer comprising mobile ions whose distribution state changes depending on the applied voltage; and A memory device comprising: a first barrier layer and a second barrier layer arranged facing each other with the electrolyte layer in between, and provided to prevent the mobile ions from diffusing out of the electrolyte layer.
2. In Article 1, A memory device further comprising a first auxiliary barrier layer provided between the electrolyte layer and the first barrier layer.
3. In Article 2, A memory device further comprising a second auxiliary barrier layer provided between the electrolyte layer and the second barrier layer.
4. In Article 1, A memory device further comprising a third auxiliary barrier layer positioned facing the electrolyte layer with the first barrier layer in between.
5. In Article 4, A memory device further comprising a fourth auxiliary barrier layer positioned facing the electrolyte layer with the second barrier layer in between.
6. In Article 1, The above mobile ion is a memory device comprising an alkali metal ion or an alkali-earth metal ion.
7. In Article 1, It further includes a second semiconductor layer, The first semiconductor layer is provided in a direction perpendicular to one surface of the second semiconductor layer, and A plurality of the gate stacks are stacked in the vertical direction above, and The above channel is a memory element shared among the plurality of gate stacks.
8. In Article 7, A memory device in which the first barrier layer, the second barrier layer, and the electrolyte layer of each of the above gate stacks are connected to each other in the vertical direction.
9. In Article 7, The first barrier layer, the second barrier layer, and the electrolyte layer of each of the above gate stacks are memory devices spaced apart from each other in the vertical direction.
10. In Article 7, A memory device in which each of the above gate stacks is configured to completely surround the first semiconductor layer, and the first barrier layer, the second barrier layer, and the electrolyte layer are concentric.
11. A step of forming a stacked structure by alternately and repeatedly depositing a sacrificial layer and an insulating layer on a substrate; A step of forming a channel hole penetrating the above-mentioned stacked structure; A step of sequentially forming a first barrier layer, an electrolyte layer containing mobile ions, and a second barrier layer on the inner surface of the channel hole; A step of filling at least a portion of the interior of the remaining channel hole with a semiconductor layer after the first barrier layer, the electrolyte layer, and the second barrier layer are formed; A step of removing the sacrificial layer to form a gate hole; and A method for manufacturing a memory device comprising the step of depositing an electrode material on the gate hole.
12. In Article 11, The second barrier layer, the electrolyte layer, and the first barrier layer are sequentially deposited on the inner surface of the channel hole in the order described above, and A method for manufacturing a memory device, further comprising the step of forming a first auxiliary barrier layer between the electrolyte layer and the first barrier layer.
13. In Article 12, A method for manufacturing a memory device, further comprising the step of forming a second auxiliary barrier layer between the electrolyte layer and the second barrier layer.
14. In Article 11, The second barrier layer, the electrolyte layer, and the first barrier layer are sequentially deposited on the inner surface of the channel hole in the order described above, and A method for manufacturing a memory device, further comprising the step of forming a third auxiliary barrier layer between the semiconductor layer and the first barrier layer.
15. In Article 14, A method for manufacturing a memory device, further comprising the step of forming a fourth auxiliary barrier layer between the electrode material and the second barrier layer.
16. In Article 11, A method for manufacturing a memory device comprising the above mobile ion, an alkali metal ion or an alkali earth metal ion.
17. A step of forming a stacked structure by alternately and repeatedly depositing a sacrificial layer and a mask layer on a substrate; A step of forming a channel hole penetrating the above-mentioned stacked structure; A step of sequentially forming a first barrier layer, an electrolyte layer containing mobile ions, and a second barrier layer on the inner surface of the channel hole; A step of filling at least a portion of the interior of the remaining channel hole with a semiconductor layer after the first barrier layer, the electrolyte layer, and the second barrier layer are formed; A step of removing the sacrificial layer and the first barrier layer, the electrolyte layer, and the second barrier layer between the sacrificial layer and the semiconductor layer to form a hole in which the semiconductor layer is exposed; A step of filling the holes where the semiconductor layer is exposed with an insulating layer; Step of removing the above mask layer; and A method for manufacturing a memory device comprising the step of depositing an electrode material at the site where the above mask layer has been removed.
18. In Article 16, A method for manufacturing a memory device comprising the above mobile ion, an alkali metal ion or an alkali earth metal ion.
19. In Article 16, A method for manufacturing a memory device, further comprising the step of forming an auxiliary barrier layer on the inside or outside of the first barrier layer and forming another auxiliary barrier layer on the inside or outside of the second barrier layer.
20. An electronic device comprising a memory element of any one of claims 1 to 10.

Description

Nonvolatile memory devices using ion redistribution and methods of manufacturing the same and electronic apparatuses including nonvolatile memory device The present disclosure relates to a memory device and a method for manufacturing the same, and more specifically, to a non-volatile memory device using ion redistribution, a method for manufacturing the same, and an electronic device including a non-volatile memory device. Semiconductor devices can be classified into memory devices and logic devices. Memory devices are devices that store data. Generally, semiconductor memory devices can be broadly classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices are memory devices in which stored data is lost when the power supply is interrupted; examples include DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). Nonvolatile memory devices are memory devices in which stored data is not lost even when the power supply is interrupted; examples include PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), and Flash Memory Devices. Furthermore, in line with the recent trend toward higher performance and lower power consumption in semiconductor memory devices, next-generation semiconductor memory devices such as MRAM (Magnetic RAM), PCRAM (Phase Change RAM), and ReRAM (Resistive RAM) are being developed. The materials constituting these next-generation semiconductor memory devices exhibit resistance values that vary depending on current, voltage, or heat, and possess the characteristic of maintaining their resistance even when the supply of current or voltage is interrupted. Research is currently underway to apply these memories in the form of VNAND (Vertical NAND). In the case of NAND flash products, which currently dominate the memory market, VNAND products are the main items due to their advantages in increasing integration density. However, as these VNAND products are gradually reaching the allowable height limits in current chip packaging, methods for scaling unit cells are being researched. In resistive VNAND utilizing resistive memory, a phenomenon occurs during operation where electrons move through a shared charge trap layer, which can degrade various memory characteristics. FIG. 1 is a cross-sectional view showing a first non-volatile memory element according to an exemplary embodiment. FIG. 2 is a cross-sectional view showing a first memory cell array including a plurality of first non-volatile memory elements according to an exemplary embodiment. FIG. 3 is a cross-sectional view showing a second memory cell array including a plurality of first non-volatile memory elements according to an exemplary embodiment. FIG. 4 is a cross-sectional view showing a second non-volatile memory element according to an exemplary embodiment. FIG. 5 is a cross-sectional view showing a third non-volatile memory element according to an exemplary embodiment. FIGS. 6 and 7 are cross-sectional views illustrating a method of operation of a non-volatile memory device according to an exemplary embodiment. FIG. 8 is a cross-sectional view showing a fourth non-volatile memory element (vertical memory cell) according to an exemplary embodiment. Figure 9 is a plan view of Figure 8 cut in the 9-9' direction. FIG. 10 is a plan view showing in detail an example of the gate stack configuration in FIG. 9. FIG. 11 is a plan view showing the case where the planar shape of the gate electrode in FIG. 9 is non-circular (e.g., square). FIG. 12 is a cross-sectional view showing a VNAND including a non-volatile memory element according to an exemplary embodiment. FIG. 13 is a cross-sectional view illustrating a cell string with a different configuration from the cell string of FIG. 12. Figure 14 is a three-dimensional view showing a cell string of 12. FIG. 15 is a cross-sectional view illustrating a VNAND having a plurality of cell strings as exemplified in FIG. 12. Figure 16 is an equivalent circuit diagram for the VNAND of Figure 15. FIGS. 17 to 21 are cross-sectional views illustrating, in steps, a first method for manufacturing a first non-volatile memory device according to an exemplary embodiment. FIGS. 22 to 30b are cross-sectional and plan views illustrating, in steps, a second manufacturing method of a non-volatile memory device according to an exemplary embodiment. FIGS. 31 to 36 are cross-sectional views showing, in steps, a part of a third manufacturing method of a non-volatile memory device according to an exemplary embodiment. FIG. 37 is a block diagram of a memory system according to one embodiment. FIG. 38 is a block diagram showing a neuromorphic device and an external device connected thereto according to an exemplary embodiment. Hereinafter, a non-volatile memory device using ion redistribution according to exemplary embodiments, a method for manufacturing the same, and an electronic device including the non-volatile memory device will be described