KR-20260065396-A - substrate processing apparatus

KR20260065396AKR 20260065396 AKR20260065396 AKR 20260065396AKR-20260065396-A

Abstract

The technical concept of the present invention provides a semiconductor substrate comprising: a base layer, a first layer located on the base layer, a second layer located on the first layer, and a plurality of alignment marks located within the first layer and the second layer; and a measuring device configured to measure the plurality of alignment marks of the semiconductor substrate; wherein each of the plurality of alignment marks includes a plurality of first alignment keys located on the first layer and a plurality of second alignment keys located on the second layer, and in a planar view, the plurality of first alignment keys extend in a first horizontal direction and are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and in a planar view, the plurality of second alignment keys extend in a third horizontal direction and are spaced apart from each other in a fourth horizontal direction perpendicular to the third horizontal direction, and a part of each of the plurality of first alignment keys and a part of each of the plurality of second alignment keys overlap in a vertical direction.

Inventors

송다인
신하철
김동욱
김동형
김일환
김정현
정은희

Assignees

삼성전자주식회사

Dates

Publication Date: 20260508
Application Date: 20241101

Claims (10)

A semiconductor substrate comprising a base layer, a first layer located on the base layer, a second layer located on the first layer, and a plurality of alignment marks located within the first layer and the second layer; and A measuring device configured to measure the plurality of alignment marks of the semiconductor substrate; comprising Each of the above plurality of alignment marks includes a plurality of first alignment keys located on the first layer and a plurality of second alignment keys located on the second layer, and From a planar perspective, the plurality of first alignment keys extend in a first horizontal direction and are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and From a planar perspective, the plurality of second alignment keys extend in a third horizontal direction and are spaced apart from each other in a fourth horizontal direction perpendicular to the third horizontal direction, and A portion of each of the plurality of first alignment keys and a portion of each of the plurality of second alignment keys overlap in a vertical direction. Substrate processing device.
In Article 1, The above third horizontal direction is the same direction as the above second horizontal direction, and The above measuring device is configured to move in a fifth horizontal direction above each of the plurality of alignment marks and to measure the plurality of first alignment keys and the plurality of second alignment keys of each of the plurality of alignment marks. The above fifth horizontal direction is inclined in the first horizontal direction with respect to the above second horizontal direction. Substrate processing device.
In Article 2, The above fifth horizontal direction is tilted 20° to 35° or 55° to 70° in the first horizontal direction with respect to the above second horizontal direction. Substrate processing device.
In Article 1, The above third horizontal direction is tilted toward the first horizontal direction relative to the above second horizontal direction, and A direction different from the above third horizontal direction, the above first horizontal direction, and the above second horizontal direction Substrate processing device.
In Paragraph 4, The above measuring device is configured to move in a fifth horizontal direction above each of the plurality of alignment marks and to measure the plurality of first alignment keys and the plurality of second alignment keys of each of the plurality of alignment marks. The above fifth horizontal direction is the same direction as one of the first to fourth horizontal directions. Substrate processing device.
In Article 1, Each of the above plurality of first alignment keys has a first width, The plurality of first alignment keys are spaced apart by a first distance from adjacent first alignment keys, and Each of the above plurality of second alignment keys has a second width, The plurality of second alignment keys are spaced apart by a second distance from adjacent second alignment keys, and The first width and the second width are the same, The above first distance and the above second distance are the same Substrate processing device.
A semiconductor substrate comprising a base layer, a first layer located on the base layer, a second layer located on the first layer, and a plurality of alignment marks located within the first layer and the second layer; and A measuring device configured to measure the plurality of alignment marks of the semiconductor substrate; comprising Each of the above plurality of alignment marks includes a plurality of first alignment keys located on the first layer and a plurality of second alignment keys located on the second layer, and Each of the above plurality of second alignment keys has a protrusion shape extending in a vertical direction, and In a planar view, each of the plurality of second alignment keys is arranged in a matrix shape comprising a plurality of rows spaced apart in a first horizontal direction and a plurality of columns spaced apart in a second horizontal direction perpendicular to the first horizontal direction. Substrate processing device.
In Article 7, Each of the above plurality of first alignment keys has a projection shape extending in a vertical direction, and From a planar perspective, the plurality of first alignment keys are arranged in a matrix shape including a plurality of rows spaced apart in the first horizontal direction and a plurality of columns spaced apart in the second horizontal direction, and The above plurality of first alignment keys are divided into a first group and a second group, and The plurality of first alignment keys included in the first group and the plurality of first alignment keys included in the second group are arranged alternately, Each of the plurality of second alignment keys overlaps in a vertical direction with each of the plurality of first alignment keys included in the first group. Substrate processing device.
In Article 7, Each of the above plurality of first alignment keys has a projection shape extending in a vertical direction, and From a planar perspective, the plurality of first alignment keys are arranged in a matrix shape including a plurality of rows spaced apart in the first horizontal direction and a plurality of columns spaced apart in the second horizontal direction, and Each of the plurality of second alignment keys is positioned in a spaced-apart space between the plurality of first alignments, so as not to overlap in a vertical direction with the plurality of first alignment keys, The above measuring device is configured to move in a fifth horizontal direction above each of the plurality of alignment marks and to measure the plurality of first alignment keys and the plurality of second alignment keys of each of the plurality of alignment marks. The above fifth direction is a direction inclined toward the first horizontal direction with respect to the above second horizontal direction, Substrate processing device.
In Article 7, From a planar perspective, the plurality of first alignment keys extend in the first horizontal direction and are spaced apart from each other in the second horizontal direction, A second alignment key positioned in the same column among the plurality of columns of the plurality of second alignment keys is located above one of the plurality of first alignment keys. Substrate processing device.

Description

Substrate processing apparatus The technical concept of the present invention relates to a substrate processing apparatus, and more specifically, to a substrate processing apparatus for processing a substrate including alignment marks. Due to the rapid advancement of the electronics industry and user demands in recent years, electronic devices are becoming smaller, more multifunctional, and larger in capacity, requiring highly integrated semiconductor chips. Consequently, research is continuously being conducted to reduce overlay errors in semiconductor chips to meet the demands for high integration. FIG. 1 is a conceptual diagram schematically showing a substrate processing apparatus according to one embodiment of the present invention. Figure 2 is a block diagram showing the control unit of the substrate processing device of Figure 1 in more detail. FIG. 3 is a schematic plan view of a semiconductor substrate according to exemplary embodiments. Figure 4 is a schematic plan view showing the alignment marks of the semiconductor substrate of Figure 3. Figure 5 is a schematic cross-sectional view obtained by cutting the alignment mark of Figure 4 along X1-X1' and Y1-Y1' of Figure 4. Figure 6 is an enlarged view schematically showing the "EX" portion of the alignment mark in Figure 4. Figure 7 is a diagram schematically illustrating the process of processing data measured by a measuring device. FIG. 8 is a schematic cross-sectional view showing a portion of an alignment mark according to exemplary embodiments. FIG. 9 is a plan view schematically showing alignment marks according to exemplary embodiments. FIG. 10 is a plan view schematically showing alignment marks according to exemplary embodiments. FIG. 11 is a schematic plan view showing alignment marks of a semiconductor substrate according to exemplary embodiments. FIG. 12 is a schematic cross-sectional view obtained by cutting the alignment mark of FIG. 11 along X2-X2' and Y2-Y2' of FIG. 11. FIG. 13 is a schematic cross-sectional view showing alignment marks cut according to exemplary embodiments. FIG. 14 is a schematic plan view showing alignment marks according to exemplary embodiments. FIG. 15 is a schematic cross-sectional view obtained by cutting the alignment mark of FIG. 14 along X4-X4' of FIG. 17. FIG. 16 is a cross-sectional view schematically showing alignment marks cut according to exemplary embodiments. Exemplary embodiments of the present invention are provided to more fully explain the invention to those skilled in the art to which the concept of the invention pertains, and the following embodiments may be modified in various different forms, and the scope of the invention is not limited to the following embodiments. Rather, these embodiments are provided to make the disclosure more faithful and complete and to fully convey the spirit of the invention to those skilled in the art. FIG. 1 is a conceptual diagram schematically showing a substrate processing device (100) according to one embodiment of the present invention. FIG. 2 is a block structure diagram showing a control unit (160) in more detail in the substrate processing device (100) of FIG. 1. FIG. 3 is a plan view schematically showing a semiconductor substrate (W) according to exemplary embodiments. Referring to FIGS. 1 and 2, the substrate processing device (100) may be an EUV exposure device. The substrate processing device (100) may include an EUV light source (110), a first optical system (120), a second optical system (130), a mask stage (140), a wafer stage (150), a control unit (160), and a measuring device (180). In the following, unless otherwise specifically defined, the direction parallel to the upper surface of the semiconductor substrate (W) is defined as the X direction, the direction perpendicular to the upper surface of the semiconductor substrate (W) is defined as the Z direction (or vertical direction), and the direction perpendicular to the X direction and the Z direction is defined as the Y direction. The horizontal direction is defined as the combined direction of the X direction and the Y direction. The EUV light source (110) can generate and output high energy density EUV light (L) within a wavelength range of about 5 nm to 50 nm. For example, the EUV light source (110) can generate and output high energy density EUV light (L) with a wavelength of 13.5 nm. The EUV light source (110) may be a plasma-based light source or a synchrotron radiation light source. Here, a plasma-based light source refers to a light source that generates plasma and utilizes light emitted by the plasma, and may include a laser-produced plasma (LPP) light source or a discharge-produced plasma (DPP) light source. The first optical system (120) may include a plurality of mirrors. For example, in a substrate processing device (100), the first optical system (120) may include two or three mirrors. For example, EUV light (L) from an EUV light source (110) may be incident on an EUV mask (M) pl