KR-20260065398-A - Nonvolatile Memory Device Performing Write Training

Abstract

A non-volatile memory device for performing write training is disclosed. The non-volatile memory device includes a plurality of memory dies connected to a controller via a first channel and configured to perform write training based on training data received from the controller. The plurality of memory dies includes a first memory die and a second memory die, each comprising non-volatile memory cells. The first memory die receives first training data from the controller in a first period, compares the first training data with first pattern data in a second period, and transmits a first pass/fail value for the first training data to the controller. The second memory die receives second training data from the controller in a second period.

Inventors

• 최성혁
• 설창규
• 설미령
• 송유석
• 이태민
• 최영돈

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260508

Application Date

20241101

Claims (20)

1. It includes a plurality of memory dies connected to a controller through a first channel and configured to perform write training based on training data received from the controller, and The above plurality of memory dies each include a first memory die and a second memory die, each including non-volatile memory cells, and The above first memory die is, In the first section, first training data is received from the controller, and In the second section following the first section, the first training data and the first pattern data are compared, and the first pass/fail value for the first training data is transmitted to the controller. The above second memory die is, A non-volatile memory device that receives second training data from the controller in the second section above.
2. In paragraph 1, The first memory die further includes a first page buffer for storing the first training data, and The above second memory die is a non-volatile memory device further comprising a second page buffer for storing the second training data.
3. In paragraph 2, the second memory die is, A non-volatile memory device characterized by comparing the second training data and the second pattern data in the third section after the second section, and transmitting a second pass/fail value for the second training data to the controller.
4. In paragraph 2, the first memory die is, Receives a first command and the first training data from the above controller, and A non-volatile memory device characterized by storing the first training data in the first page buffer in response to the first command.
5. In paragraph 2, the first memory die is, Receive a second command from the above controller, and A non-volatile memory device characterized by comparing the first training data and the first pattern data in response to the second command above.
6. In paragraph 5, the first memory die is, A first pattern generator that generates the first pattern data in response to the second command; and A non-volatile memory device further comprising a comparator that compares the first training data received from the page buffer and the first pattern data received from the pattern generator in response to the second command.
7. In paragraph 6, A non-volatile memory device characterized in that the first pattern generator includes a linear feedback shift register.
8. In paragraph 2, the first memory die is, Receive a third command from the above controller, and A non-volatile memory device characterized by transmitting the first pass/fail value to the controller in response to the third command.
9. In paragraph 1, The above first training data corresponds to the first delay value, and The above second training data corresponds to the above first delay value, and The above first memory die is, A non-volatile memory device that receives third training data corresponding to a second delay value different from the first delay value from the controller in a third section after the second section above.
10. In Paragraph 9, It further includes a data strobe pin that receives a data strobe signal from the above controller, and The first training data is a training pattern having a delay corresponding to the first delay value relative to the data strobe signal, and A non-volatile memory device characterized in that the third training data is a training pattern having a delay corresponding to the second delay value relative to the data strobe signal.
11. In paragraph 1, A command/address pin that receives a command and an address from the above controller via a command/address signal line; A data pin that receives data from the above controller through a data signal line; and It further includes a data strobe pin that receives a data strobe signal from the controller through a data strobe line, and The above first and second training data are received through the data pin, and A non-volatile memory device characterized in that the first pass/fail value is transmitted through the command/address pin.
12. In paragraph 1, A data pin that receives commands, addresses, and data from the above controller via a data signal line; and It further includes a data strobe signal pin that receives a data strobe signal from the controller through a data strobe line, and The above first and second training data are received through the data pin, and A non-volatile memory device characterized in that the above first pass/fail value is transmitted through the data pin.
13. A buffer chip connected to the controller via the first channel; and It includes a plurality of memory dies connected to the buffer chip through a second channel and performing first write training between the controller and the buffer chip during a first write training period, The above plurality of memory dies are, A first memory die that receives first training data corresponding to a first delay value from the controller through the buffer chip during the first section of the first writing training section; and It includes a second memory die that receives second training data corresponding to a second delay value different from the first delay value from the controller through the buffer chip during the second section of the first writing training section, and The above first memory die is, A non-volatile memory device that generates a first pass/fail value for the first training data during the second section of the first entry training section and transmits the first pass/fail value to the controller through the buffer chip.
14. In paragraph 13, the above second memory die is, A non-volatile memory device that, after the second section of the first entry training section, generates a second pass/fail value for the second training data and transmits the second pass/fail value to the controller through the buffer chip.
15. In Paragraph 14, The above first memory die is, A first page buffer storing the above-mentioned first training data; A first pattern generator that generates first pattern data; and It includes a first comparator that generates the first pass/fail value by comparing the first training data and the first pattern data, and The above second memory die is, A second page buffer storing the above second training data; A second pattern generator that generates second pattern data; and A non-volatile memory device comprising a second comparator that generates the second pass/fail value by comparing the second training data and the second pattern data.
16. In Paragraph 13, The plurality of memory dies further perform a second write training between the buffer chip and the plurality of memory dies during a second write training period, and During the first section of the second writing training section, the first memory die receives third training data from the controller through the buffer chip, and During the second section of the second writing training section, the first memory die generates a third pass/fail value for the third training data, and the second memory die receives the fourth training data from the controller through the buffer chip, and A non-volatile memory device characterized in that, during the third section of the second writing training section, the first memory die receives fifth training data from the controller through the buffer chip, and the second memory die generates a fourth pass/fail value for the fourth training data.
17. In Paragraph 16, The above third training data and the above fourth training data each correspond to the third delay value, and A non-volatile memory device characterized in that the above-mentioned fifth training data corresponds to a fourth delay value different from the above-mentioned third delay value.
18. It includes a plurality of memory dies connected to a controller through a first channel and performing write training based on training data received from the controller, The above plurality of memory dies are, A first memory die including a first page buffer, storing reference training data and first training data received from the control in the first page buffer, and generating a first pass/fail value for the first training data based on the result of a logical operation on the reference training data and the first training data; and A second memory die comprising a second page buffer, storing the reference training data and the second training data received from the control in the second page buffer, and generating a second pass/fail value for the second training data based on the result of a logical operation on the reference training data and the second training data, A non-volatile memory device characterized in that while the first memory die generates the first pass/fail value, the second memory die receives the reference training data or the second training data.
19. In paragraph 18, the above-mentioned first memory die is, During the first interval, the reference training data is received, and the reference training data is stored in the first area of the first page buffer, and During the second interval, the reference training data stored in the first area of the first page buffer is dumped into the second area of the first page buffer, and During the third interval, the first training data is received, and the first training data is stored in the first area of the first page buffer, and A non-volatile memory device characterized by generating the first pass/fail value by counting the result of a logical operation on the reference training data and the first training data during the fourth interval.
20. In paragraph 19, the above-mentioned second memory die is, During the above fourth interval, the reference training data is received, and the reference training data is stored in the first area of the second page buffer, and During the fifth interval, the reference training data stored in the first area of the second page buffer is dumped into the second area of the first page buffer, and During the 6th interval, the second training data is received, and the second training data is stored in the first area of the second page buffer, and During the 7th interval, the second pass/fail value is generated by counting the result of a logical operation on the reference training data and the second training data, and A non-volatile memory device characterized in that the first memory die receives third training data during the seventh interval.

Description

Nonvolatile Memory Device Performing Write Training The technical concept of the present disclosure relates to a memory device, and more specifically, to a non-volatile memory device that performs write training and a method for write training of a non-volatile memory. A storage device may include non-volatile memory and a controller that controls the non-volatile memory. Since the non-volatile memory and the controller have different operational characteristics, initialization or training may be required during the initial operation of the storage device or during the initial operation between the non-volatile memory and the controller. In particular, training operations may be performed to ensure the reliability of data transmitted and received between the non-volatile memory and the controller. Since data is transmitted and received between the non-volatile memory and the controller based on training parameters obtained through the training operation, it may be important to obtain accurate training parameters. FIG. 1 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 2 is a block diagram showing a memory die according to one embodiment of the present disclosure. FIG. 3 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 4 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 5 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 6 is a timing diagram showing the write training operation of the first and second memory dies of FIG. 5 according to one embodiment of the present disclosure. FIG. 7 is a timing diagram showing an example of a write training operation of the first and second memory dies of FIG. 5 according to one embodiment of the present disclosure. FIG. 8 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 9 is a timing diagram showing the write training operation of the first and second memory dies of FIG. 8 according to one embodiment of the present disclosure. FIG. 10 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 11 is a timing diagram showing the write training operation of the first to fourth memory dies of FIG. 10 according to one embodiment of the present disclosure. FIG. 12 is a timing diagram showing an example of a write training operation of the first to fourth memory dies of FIG. 10 according to one embodiment of the present disclosure. FIGS. 13a and FIGS. 13b are timing diagrams showing other examples of write training operations of the first to fourth memory dies of FIG. 10 according to one embodiment of the present disclosure. FIG. 14 is a timing diagram showing another example of a write training operation of the first to fourth memory dies of FIG. 10 according to one embodiment of the present disclosure. FIG. 15 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 16 is a timing diagram showing an example of a write training operation of the first to fourth memory dies of FIG. 15 according to one embodiment of the present disclosure. FIG. 17 is a timing diagram showing another example of a write training operation of the first to fourth memory dies of FIG. 15 according to one embodiment of the present disclosure. FIG. 18 is a block diagram showing a controller according to one embodiment of the present disclosure. FIG. 19 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 20 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 21 is a timing diagram showing the write training operation of the first and second memory dies of FIG. 20 according to one embodiment of the present disclosure. FIG. 22 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 23 is a timing diagram showing an example of a write training operation of the first to fourth memory dies of FIG. 22 according to one embodiment of the present disclosure. FIG. 24 is a block diagram showing a memory die according to one embodiment of the present disclosure. FIG. 25 is a block diagram showing a storage device according to one embodiment of the present disclosure. FIG. 26 is a timing diagram showing the write training operation of the first and second memory dies of FIG. 25 according to one embodiment of the present disclosure. FIG. 27 is a flowchart illustrating a method of operation of a non-volatile memory according to one embodiment of the present disclosure. FIG. 28 is a flowchart illustrating a method of operation between a controller, a first memory die, and a second memory die according to one embodiment of the present disclosure. FIG. 29 is a flowchart illustrating a method of operation of a non-vol