Search

KR-20260065438-A - Memory System

KR20260065438AKR 20260065438 AKR20260065438 AKR 20260065438AKR-20260065438-A

Abstract

A memory media comprising: a substrate having a first substrate side and a second substrate side facing the first substrate side; and a first memory stack mounted on the substrate. The substrate includes first signal substrate pads exposed on a surface. The first signal substrate pads are positioned closer to the first substrate side than to the second substrate side. The first memory stack includes a first memory chip and a second memory chip offset stacked on the first memory chip. The first memory chip includes first outer chip pads and first inner chip pads positioned adjacent to the first chip side of the first memory chip. The first chip side of the first memory chip is closer to the first substrate side of the substrate than to the second substrate side of the substrate. The first outer chip pads are closer to the first chip side of the first memory chip than to the first inner chip pads. The second memory chip includes second outer chip pads and second inner chip pads positioned adjacent to the first chip side of the second memory chip. The first chip side of the second memory chip is closer to the first substrate side than to the second substrate side of the substrate. The second outer chip pads are positioned closer to the first chip side of the second memory chip than to the second inner chip pads. The corresponding first signal substrate pads, the corresponding first inner chip pads, and the corresponding second inner chip pads are electrically connected.

Inventors

  • 이성주

Assignees

  • 에스케이하이닉스 주식회사

Dates

Publication Date
20260508
Application Date
20241114
Priority Date
20241101

Claims (18)

  1. A substrate having a first substrate side and a second substrate side facing the first substrate side; and A memory media comprising a first memory stack mounted on the above substrate, and The above substrate includes first signal substrate pads exposed on a surface, and the first signal substrate pads are positioned closer to the first substrate side than to the second substrate side, and The first memory stack includes a first memory chip and a second memory chip offset stacked on the first memory chip, and The first memory chip includes first outer chip pads and first inner chip pads arranged adjacent to the first chip side of the first memory chip, and the first chip side of the first memory chip is closer to the first substrate side of the substrate than to the second substrate side of the substrate, and The first outer chip pads are positioned closer to the first chip side of the first memory chip than the first inner chip pads, and The second memory chip includes second outer chip pads and second inner chip pads arranged adjacent to the first chip side of the second memory chip, and the first chip side of the second memory chip is closer to the first substrate side than the second substrate side of the substrate, and The second outer chip pads are positioned closer to the first chip side of the second memory chip than the second inner chip pads, and A memory system in which the corresponding first signal substrate pads, the corresponding first inner chip pads, and the corresponding second inner chip pads are electrically connected.
  2. In paragraph 1, The first outer chip pads and the second outer chip pads are a floating memory system.
  3. In paragraph 1, The above first memory stack is: A third memory chip offset stacked on the second memory chip; and It includes a fourth memory chip offset stacked on the third memory chip, and The third memory chip includes third outer chip pads and third inner chip pads arranged adjacent to the first chip side of the third memory chip, and the first chip side of the third memory chip is closer to the first substrate side than the second substrate side of the substrate, and The third outer chip pads are positioned closer to the first chip side of the third memory chip than the third inner chip pads, and The fourth memory chip includes fourth outer chip pads and fourth inner chip pads arranged adjacent to the first chip side of the fourth memory chip, and the first chip side of the fourth memory chip is closer to the first substrate side than the second substrate side of the substrate, and The fourth outer chip pads are positioned closer to the first chip side of the fourth memory chip than the fourth inner chip pads, and A memory system in which the corresponding signal substrate pads, the corresponding first inner chip pads, the corresponding second inner chip pads, the corresponding third inner chip pads, and the corresponding fourth inner chip pads are electrically connected.
  4. In paragraph 3, The above third outer chip pads and the above fourth outer chip pads are floating memory systems.
  5. In paragraph 3, The substrate further comprises first to fourth power substrate pads exposed on the surface, and the first to fourth power substrate pads are closer to the second substrate side than to the first substrate side, and The first memory chip further includes first power chip pads arranged adjacent to the second chip side of the first memory chip facing the first chip side of the first memory chip, and The second memory chip further includes second power chip pads arranged adjacent to the second chip side of the second memory chip facing the first chip side of the second memory chip, and The third memory chip further includes third power chip pads arranged adjacent to the second chip side of the third memory chip facing the first chip side of the third memory chip, and The fourth memory chip further includes fourth power chip pads arranged adjacent to the second chip side of the fourth memory chip facing the first chip side of the fourth memory chip, and The first power substrate pads and the first power chip pads are electrically connected, The second power substrate pads and the second power chip pads are electrically connected, The third power substrate pads and the third power chip pads are electrically connected, and A memory system in which the above-mentioned fourth power board pads and the above-mentioned fourth power chip pads are electrically connected.
  6. In paragraph 1, Memory controller; Interface circuit; First parallel data channels between the memory controller and the interface circuit; and A memory system further comprising second parallel data channels between the interface circuit and the memory media.
  7. In paragraph 6, The first parallel data channels mentioned above include DDR PHY Interface (DFI) channels, and The above second parallel data channels are a memory system including Global Input/Output (GIO) channels.
  8. In paragraph 6, The above memory media further includes a second memory stack, and The above substrate includes second signal substrate pads exposed on the surface, and The second signal substrate pads are positioned closer to the first substrate side of the substrate than to the second substrate side of the substrate, and The above second signal substrate pads are a memory system electrically connected to the above second memory stack.
  9. In paragraph 6, The above substrate further includes first signal substrate wirings and second signal substrate wirings, and The above first signal board wirings are electrically connected to the corresponding first signal board pads, and The above second signal board wirings are electrically connected to the corresponding second signal board pads, and The second parallel data channels include a first set of the second parallel data channels and a second set of the second parallel data channels, and The first signal board wirings and the second parallel data channels of the first set are electrically connected, and A memory system in which the second signal board wirings and the second set of second parallel data channels are electrically connected.
  10. In Paragraph 9, A memory system in which the number of the first parallel data channels is equal to the sum of the number of the second parallel data channels of the first set and the number of the second parallel data channels of the second set.
  11. Memory controller; Interface circuit; DDR PHY Interface (DFI) channels between the memory controller and the interface circuit; Memory media; and It includes global input/output (GIO) channels between the interface circuit and the memory system, and The above memory media includes a first memory stack and a second memory stack mounted on a substrate, and The first and second memory stacks each include first memory chips and second memory chips offset stacked on the substrate, and The above substrate is: First signal board wirings and second signal board wirings electrically connected to the above global input/output channels, respectively; First signal substrate pads electrically connected to the first signal substrate wirings; and It includes second signal board pads electrically connected to the second signal board wirings, and Each of the first memory chips includes first outer chip pads and first inner chip pads disposed close to the first chip side of the first memory chip, and the first outer chip pads are disposed closer to the first chip side of the first memory chip than the first inner chip pads, and Each of the above-mentioned second memory chips includes second outer chip pads and second inner chip pads disposed close to the first chip side of the second memory chip, and the second outer chip pads are disposed closer to the first chip side of the second memory chip than the second inner chip pads, and The first signal substrate pads and the first and second inner chip pads of the first and second memory chips of the first memory stack are each electrically connected, and A memory system in which the second signal substrate pads and the first and second inner chip pads of the first and second memory chips of the second memory stack are each electrically connected.
  12. In Paragraph 11, A memory system comprising a plurality of data channels, each of which is connected in parallel, wherein the above DFI channels and the above GIO channels are respectively connected in parallel.
  13. In Paragraph 12, The number of data channels of the above DFI channels and the number of data channels of the above GIO channels are the same memory system.
  14. In Paragraph 13, A memory system comprising a first set of GIO channels electrically connected to the first memory stack and a second set of GIO channels electrically connected to the second memory stack.
  15. In Paragraph 11, The first and second outer chip pads of the first and second memory chips of the first and second memory stacks are a floating memory system.
  16. In Paragraph 11, The above substrate further includes power substrate pads, and The first and second memory chips of the first and second memory stacks further include power chip pads positioned close to the second chip sides facing the first chip sides, and A memory system in which the power board pads and the power chip pads are electrically connected.
  17. In Paragraph 11, The above first memory chips are: First lower memory chip; A first intermediate memory chip offset stacked on the first lower memory chip; and It includes a first upper memory chip offset stacked on the first intermediate memory chip, and The above outer chip pads are: First lower outer chip pads positioned close to the first chip side of the first lower memory chip; First intermediate outer chip pads positioned close to the first chip side of the first intermediate memory chip; and It includes first upper outer chip pads positioned close to the first chip side of the first upper memory chip, and The above inner chip pads are: First lower inner chip pads positioned close to the first chip side of the first lower memory chip; First intermediate inner chip pads positioned close to the first chip side of the first intermediate memory chip; and It further includes first upper inner chip pads positioned close to the first chip side of the first upper memory chip, and The first lower outer chip pads are closer to the first chip side of the first lower memory chip than the first lower inner chip pads; The first intermediate outer chip pads are closer to the first chip side of the first intermediate memory chip than the first intermediate inner chip pads; and The first upper outer chip pads are closer to the first chip side of the first upper memory chip than the first upper inner chip pads, and A memory system in which the corresponding first signal substrate pads, the corresponding first lower inner chip pads, the corresponding first intermediate inner chip pads, and the corresponding first upper inner chip pads are electrically connected.
  18. In Paragraph 17, The above second memory chips are: Second lower memory chip; A second intermediate memory chip offset stacked on the second lower memory chip; and It includes a second upper memory chip offset stacked on the second intermediate memory chip, and The above outer chip pads are: Second lower outer chip pads positioned close to the side of the first chip of the second lower memory chip; Second intermediate outer chip pads positioned close to the side of the first chip of the second intermediate memory chip; and It further includes second upper outer chip pads positioned close to the side of the first chip of the second upper memory chip, and The above inner chip pads are: Second lower inner chip pads positioned close to the side of the first chip of the second lower memory chip; Second intermediate inner chip pads positioned close to the side of the first chip of the second intermediate memory chip; and It further includes second upper inner chip pads positioned close to the side of the first chip of the second upper memory chip, and The second lower outer chip pads are closer to the first chip side of the second lower memory chip than the second lower inner chip pads; The second intermediate outer chip pads are closer to the first chip side of the second intermediate memory chip than the second intermediate inner chip pads; and The second upper outer chip pads are closer to the first chip side of the second upper memory chip than the second upper inner chip pads. A memory system in which the corresponding second signal substrate pads, the corresponding second lower inner chip pads, the corresponding second intermediate inner chip pads, and the corresponding second upper inner chip pads are electrically connected.

Description

Memory System The present disclosure relates to a memory system comprising a controller and a memory stack. Various memory systems for high-speed operation and low power consumption are being researched. Figure 1 is a block diagram schematically showing the electronic system of the present invention. FIG. 2 is a block diagram schematically showing a CXL controller according to one embodiment of the present disclosure. FIG. 3 is a block diagram schematically showing a memory media according to one embodiment of the present disclosure. FIG. 4 is a diagram schematically showing data channels for data communication in a memory system according to one embodiment of the present disclosure. FIGS. 5a and 5b are a top view and a side view schematically showing a memory stack according to one embodiment of the present disclosure. FIG. 6 is a diagram schematically showing a memory system according to embodiments of the present disclosure. FIG. 7 is a diagram illustrating that a first memory chip operates in slave mode according to one embodiment of the present disclosure. In the present disclosure, "to communicate" may be interpreted to mean transmitting and receiving electrical signals to and from each other. That is, "not to communicate" may be interpreted to mean not transmitting and receiving electrical signals to and from each other. In the present disclosure, the descriptions "close to or adjacent to the first substrate side" and "close to or adjacent to the second substrate side" may be interpreted to mean "closer to or adjacent to the first substrate side than the second substrate side" and "closer to or adjacent to the second substrate side than the first substrate side." In the present disclosure, the descriptions "close to or adjacent to the first chip side" and "close to or adjacent to the second chip side" may be interpreted to mean "closer to or adjacent to the first chip side than the second chip side" and "closer to or adjacent to the second chip side than the first chip side." FIG. 1 is a block diagram schematically showing an electronic system (1000) of the present invention. Referring to FIG. 1, an electronic system (1000) according to one embodiment of the present disclosure may include a host (900) and a memory system (800). The host (900) may include one of a server, a processor, or a computing system. The processor may include at least one of a processing unit such as a central processing unit (CPU), a graphic processing unit (GPU), an application processor (AP), a micro control unit (MCU), and a neural processing unit (NPU). The host (900) and the memory system (800) may communicate electrically through external channels (eCH). In one embodiment, the external channels (eCH) may include Compute eXpress Link (CXL) channels. The memory system (800) may include a CXL controller (600) and a memory media (700). The CXL controller (600) may receive various signals and data from a host (900) and transmit them to the memory media (700), and may receive data from the memory media (700) and transmit it to the host (900). The memory system (800) may further include internal channels (iCH) that electrically connect the CXL controller (600) and the memory media (700). The CXL controller (600) and the memory media (700) may electrically communicate with each other through the internal channels (iCH). The internal channels (iCH) may include data channels that transmit chip select signals, data strobe signals, and data signals. The memory system (800) may further include a CA (command/address) channel that electrically connects the CXL controller (600) and the memory media (700). FIG. 2 is a block diagram schematically showing a CXL controller (600) according to one embodiment of the present disclosure. Referring to FIG. 2, the CXL controller (600) according to one embodiment of the present disclosure may include an external interface circuit (610), a CXL block (620), a memory controller (630), and an internal interface circuit (640). The external interface circuit (610) may include a PCIe (Peripheral Component Interconnect Express) serializer/deserializer (Ser/Des) and a transceiver/receiver (TX/RX). The CXL block (620) may provide a low-latency and high-bandwidth memory access environment. In one embodiment, the CXL block (620) may be CXL 2.0. The memory controller (630) may exchange various signals and data to operate the memory media (700). The memory controller (630) and the memory media (700) can exchange all data signals in parallel at the same time through internal channels (iCH). The CXL block (620) can store the base address of BARs (base address registers) and HDM (Host-managed-Device-Memory) within the configured space. The CXL block (620) can convert a CXL packet received through the external interface circuit (610) into a memory request and transmit the memory request to the memory controller (630). The CXL block (620) can generate an internal memory address based on the base address of the HDM in