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KR-20260065483-A - Capacitor-less memory device

KR20260065483AKR 20260065483 AKR20260065483 AKR 20260065483AKR-20260065483-A

Abstract

A capacitorless memory device according to one aspect of the present invention may include a memory cell comprising a write transistor including a first gate, a first drain, and a first source, and a read transistor including a second gate, a second drain, a second source, and a back gate, wherein the second drain is connected to the first drain and the second gate is connected to the first source to operate as a storage node. A bit line may be connected in common to the first drain and the second drain, a word line may be connected to the first gate, and a control line may be connected to the back gate. The read transistor may be turned on or turned off depending on the data state of the storage node or a control voltage applied to the control line.

Inventors

  • 강대환
  • 류용우

Assignees

  • 포항공과대학교 산학협력단

Dates

Publication Date
20260508
Application Date
20250702
Priority Date
20241101

Claims (19)

  1. A write transistor comprising a first gate, a first drain, and a first source; and A memory cell comprising a read transistor including a second gate, a second drain, a second source, and a back gate, wherein the second gate is connected to the first source and operates as a storage node; A bit line commonly connected to the first drain and the second drain; A word line connected to the first gate; and It includes a control line connected to the above back gate, The above read transistor is turned on or turned off depending on the data state of the storage node or the control voltage applied to the control line. Capacitorless memory device.
  2. In Article 1, To store a first data state in the storage node of the memory cell, a write operation voltage is applied to the bit line and the word line, and a pre-charge voltage or an off voltage is applied to the control line. Capacitorless memory device.
  3. In Article 1, In order to store a second data state in the storage node of the memory cell, a write operation voltage is applied to the word line, an off voltage is applied to the bit line, and a pre-charge voltage or an off voltage is applied to the control line. Capacitorless memory device.
  4. In Article 1, To read the data state of the memory cell, an off voltage is applied to the word line and the control line, and the degree of voltage drop is detected in the bit line. Capacitorless memory device.
  5. In Article 1, A capacitorless memory element further comprising a selection line connected to the second source.
  6. In Article 5, In order to store a first data state in the storage node of the memory cell, the bit line and the word line write operation voltages are applied, the off voltage or pre-charge voltage is applied to the control line, and the pre-charge voltage or write operation voltage is applied to the select line. Capacitorless memory device.
  7. In Article 5, In order to store a second data state in the storage node of the memory cell, a write operation voltage is applied to the word line, an off voltage is applied to the bit line, an off voltage or a pre-charge voltage is applied to the control line, and a pre-charge voltage or an off voltage is applied to the select line. Capacitorless memory device.
  8. In Article 1, To read the data state of the memory cell, an off voltage is applied to the word line and the control line, an off voltage is applied to the select line, and the degree of voltage drop is detected in the bit line. Capacitorless memory device.
  9. A plurality of vertically stacked write transistors, each comprising a first gate, a first drain, and a first source; and a plurality of vertically stacked memory cells, each comprising a second gate, a second drain, a second source, and a back gate, wherein the second gate is connected to the first source to operate as a storage node, and each comprising a plurality of read transistors vertically connected to each other; A bit line connected to the first drain of the plurality of memory cells and connected to the second drain of the uppermost read transistor among the plurality of read transistors; A plurality of word lines each connected to the first gate of the plurality of memory cells; A plurality of control lines each connected to the back gates of the plurality of memory cells; and It includes a select line connected to the second source of the lowest layer read transistor among the plurality of read transistors, The above read transistor is turned on or turned off depending on the data state of the storage node or the control voltage applied to the back gate. Capacitorless memory device.
  10. In Article 9, In order to store a first data state in the storage node of a memory cell selected among the plurality of memory cells, a write operation voltage is applied to the bit line, a write operation voltage is applied to the word line connected to the memory cell selected among the plurality of word lines and an off voltage is applied to the remaining word lines, an off voltage or a pre-charge voltage is applied to the control line, and a pre-charge voltage or a write operation voltage is applied to the selection line. Capacitorless memory device.
  11. In Article 9, In order to store a second data state in the storage node of a memory cell selected among the plurality of memory cells, an off voltage is applied to the bit line, a write operation voltage is applied to the word line connected to the memory cell selected among the plurality of word lines and an off voltage is applied to the remaining word lines, an off voltage or a pre-charge voltage is applied to the control line, and a pre-charge voltage or an off voltage is applied to the selection line. Capacitorless memory device.
  12. In Article 9, To read the data state of a selected memory cell among the plurality of memory cells, an off voltage is applied to the plurality of word lines, an off voltage is applied to a control line connected to the back gate of the selected memory cell among the plurality of control lines, a pre-charge voltage is applied to the remaining control lines, an off voltage is applied to the selection line, and the degree of voltage drop in the bit line is detected. Capacitorless memory device.
  13. A plurality of first semiconductor layers stacked spaced apart from each other on a substrate; A plurality of first gate electrode layers disposed between the plurality of first semiconductor layers; A first gate insulating layer between the plurality of first semiconductor layers and the plurality of first gate electrode layers; A plurality of first drain electrode layers, each connected to one side of the plurality of first semiconductor layers; A plurality of first source electrode layers, each connected to the other side of the plurality of first semiconductor layers; A plurality of second gate electrode layers, each connected to the plurality of first source electrode layers; A second semiconductor layer extending vertically across the plurality of second gate electrode layers; A plurality of back gate electrode layers, each disposed on the opposite side of the plurality of second gate electrode layers of the second semiconductor layer; A second gate insulating layer disposed between the plurality of second gate electrode layers and the second semiconductor layer and between the plurality of back gate electrode layers and the second semiconductor layer; A plurality of word lines each connected to the plurality of first gate electrode layers; and A bit line connected to the plurality of first drain electrode layers and connected to the top of the second semiconductor layer, and The plurality of second gate electrode layers are each used as a plurality of storage nodes, Capacitorless memory device.
  14. In Article 13, The above bit line is, A vertical electrode extended vertically to be connected to the plurality of first drain electrode layers; and A horizontal electrode extending horizontally to be connected to the top of the second semiconductor layer and including a horizontal electrode connected to the vertical electrode, Capacitorless memory device.
  15. In Article 13, Among the plurality of first source electrode layers and the plurality of second gate electrode layers, the first source electrode layer and the second gate electrode layer disposed on the same layer are integrally formed with each other. Capacitorless memory device.
  16. In Article 13, In the second semiconductor layer, the portions facing the plurality of second gate electrode layers function as channel layers, and The portions between the second channel layers in the second semiconductor layer function as second drain electrode layers or second source electrode layers. Capacitorless memory device.
  17. In Article 13, The plurality of first semiconductor layers each have a planar shape, and The second semiconductor layer has a pillar shape, Capacitorless memory device.
  18. In Article 13, The plurality of first semiconductor layers and the second semiconductor layer comprise an oxide semiconductor material. Capacitorless memory device.
  19. In Article 13, An interlayer insulating layer on the above substrate; and Further comprising via electrodes formed within the interlayer insulating layer and connecting the substrate and the lower end of the second semiconductor layer or connecting the substrate and the bit line, Capacitorless memory device.

Description

Capacitor-less memory device The present invention relates to a semiconductor device, and more specifically, to a memory device capable of storing data without a capacitor. Generally, memory devices can be divided into volatile devices, which lose data when the power is turned off, and non-volatile devices, which retain data even when the power is off. Among volatile devices, DRAM typically uses capacitors to store data, and research is underway to increase data capacity by increasing the capacitance of these capacitors. A standard DRAM device consists of a memory cell made up of one transistor and one capacitor (1T-1C). However, in DRAM devices, as the volume of the capacitor increases, there are limitations to increasing integration density and the difficulty of manufacturing increases significantly. Accordingly, research is being conducted on capacitor-less DRAM, which can operate like a standard DRAM device without a capacitor. Conventionally, capacitorless DRAM devices implement memory operation using two transistors (2T-0C) without capacitors. However, when implementing the device in a planar type, a large cell area is still required, and the process of stacking in three dimensions to increase the integration density is also difficult. Additionally, while implementing the device in a vertical type has the advantage of reducing the area, the process of stacking in three dimensions to increase the integration density is also difficult. FIG. 1 is a schematic circuit diagram showing a capacitorless memory element according to one embodiment of the present invention. Figure 2 is a time chart that exemplarily shows the operation of the capacitorless memory device of Figure 1. Figure 3 is a graph showing the bit line voltage change during a read operation of the capacitorless memory device of Figure 1. FIG. 4 is a schematic circuit diagram showing a capacitorless memory element according to another embodiment of the present invention. FIGS. 5 to 10 are schematic circuit diagrams showing the operation methods of the capacitorless memory device of FIG. 4. FIGS. 11a and FIGS. 11b are schematic perspective views of a capacitorless memory element according to another embodiment of the present invention, viewed from the front and rear. FIG. 12 is a schematic cross-sectional view of the capacitorless memory device of FIG. 11a and FIG. 11b. Hereinafter, several preferred embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments of the present invention are provided to more fully explain the invention to those skilled in the art, and the following embodiments may be modified in various different forms, and the scope of the invention is not limited to the following embodiments. Rather, these embodiments are provided to make the disclosure more faithful and complete and to fully convey the spirit of the invention to those skilled in the art. In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity of explanation. FIG. 1 is a schematic circuit diagram showing a capacitorless memory element (100) according to one embodiment of the present invention. Referring to FIG. 1, the capacitorless memory device (100) may include a memory cell (MC). The memory device (100) can process data using the memory cell (MC), and the memory cell (MC) can store and read data without a capacitor. The memory device (100) may include a dynamic random access memory (DRAM) device. More specifically, the memory cell (MC) may include a write transistor (TR1) and a read transistor (TR2). The write transistor (TR1) may include a first gate (G1), a first drain (D1), and a first source (S1), and the read transistor (TR2) may include a second gate (G2), a second drain (D2), a second source (S2), and a back gate (G3). For example, the write transistor (TR1) and the read transistor (TR2) may be provided as metal oxide field-effect transistors (MOSFETs). In the memory cell (MC), the second gate (G2) of the read transistor (TR2) can be connected to the first source (S1) of the write transistor (TR1) to operate as a storage node (SN). For example, the first source (S1) and the second gate (G2) may be separated but can be interpreted as being connected to each other. As another example, the first source (S1) and the second gate (G2) may be integrated and not separated from each other, and may perform the functions of the first source (S1) and the second gate (G2) simultaneously. In this case, the first source (S1) and the second gate (G2) are not referred to separately but may be collectively referred to as one of the two or referred to as a storage node (SN). The bit line (BL) can be commonly connected to the first drain (B1) of the write transistor (TR1) and the second drain (D2) of the read transistor (TR2). Thus, the same operation signal can be applied to the first drain (D1) and the second drain (D2) through the bit line (BL). This structur