KR-20260065557-A - SILICON CARBIDE TRANSISTOR WITH INTERRUPTED SOURCE CONTACTS

Abstract

A transistor comprises a substrate having an active region having a first conductivity type. At least one stripe region is disposed within the active region, and each stripe region includes a well region, a source region, trenches, and a source conductor. The well region has a second conductivity type and a first depth, and the source region is disposed within the well region, has a first conductivity type, and has a second depth smaller than the first depth. The trenches are spaced apart from each other and extend into the well region through the source region, and each trench includes at least one sidewall. And, the source conductor is disposed within each trench and is electrically coupled to the source region at one or more sidewalls and is electrically coupled to the well region.

Inventors

• 순다레산, 시다르스
• 박, 재훈
• 월시, 나다니엘

Assignees

• 나비타스 세미컨덕터 리미티드

Dates

Publication Date

20260508

Application Date

20251030

Priority Date

20241101

Claims (20)

1. As a transistor device, A semiconductor substrate having an active region of the first conductivity type; It includes at least one stripe region disposed within the above active region, and each of the stripe regions is, A second challenge type well region having a first depth; A second conductivity type source region disposed within the well region and having a second depth smaller than the first depth; Trenchs spaced apart from each other, extending into the well region through the source region, and each having at least one sidewall; and A transistor element comprising a source conductor disposed within each of the above trenches and electrically coupled to the source region through at least one of the at least one sidewall and electrically coupled to the well region.
2. In paragraph 1, The above first conductivity type is N-type; The above second conductivity type is a P-type transistor device.
3. A transistor element according to claim 1, further comprising a resistance contact disposed between the source conductor and one or more of the sidewalls of each of the at least one trench.
4. In paragraph 1, A first resistance contact disposed between one or more of the sidewalls of each of the above-mentioned at least one trench and the source conductor; and A transistor element further comprising a second resistance contact disposed between one or more of the other sidewalls of each of the at least one trench and the source conductor.
5. In paragraph 4, the transistor element, wherein the first resistance contact portion has a different composition from the second resistance contact portion.
6. A transistor element according to claim 1, wherein the trenches are spaced apart from each other by a spacing distance.
7. A transistor element according to claim 1, wherein each of the above trenches has at least one rounded corner.
8. In paragraph 1, The above well region has a first length and a first width; A transistor element having a source region having a second length shorter than the first length and a second width narrower than the first width.
9. A transistor element according to claim 1, wherein at least one of the side walls of each of the at least one trench is inclined toward the interior of the trench such that the width and length of the trench are greater at the upper surface of the trench than at the lower surface of each trench.
10. A transistor element according to claim 1, wherein each of the trenches includes at least one rounded corner at the bottom of the trench.
11. A transistor element according to claim 1, wherein each stripe region further comprises a first sinker region having the second conductivity type disposed within the active region below the trench.
12. A transistor device according to claim 11, wherein each stripe region further comprises a second sinker region having the second conductivity type disposed within the active region adjacent to the well region and the first sinker region.
13. A transistor element according to claim 1, further comprising a plurality of stripe regions having a pitch.
14. In paragraph 1, each of the stripe regions is, A gate insulator positioned over a portion of the well region adjacent to the upper surface of the substrate; A conductive gate disposed over the gate insulator; and A transistor device further comprising an interlayer dielectric disposed between the gate and the source conductor.
15. A transistor device according to claim 1, wherein each of the stripe regions further comprises a charge diffusion layer disposed within the active region adjacent to the well region.
16. A transistor device according to claim 1, wherein each of the stripe regions further comprises a charge diffusion layer disposed within the active region adjacent to the second sinker region.
17. In claim 11, the source contact is a transistor element electrically coupled to the well region through the first sinker region.
18. In claim 12, the source contact is a transistor element electrically coupled to the well region through the second sinker region.
19. In claim 1, the semiconductor substrate comprises a SiC semiconductor substrate, forming a transistor device.
20. A method for forming a transistor element, wherein in each of at least one stripe region of an active region having a first conductivity type of a substrate, A step of forming a well region having a second conductivity type, a first length, a first width, and a first depth; A step of forming a source region within the well region having the first conductivity type, a second length, a second width, and a second depth smaller than the first depth; A step of forming a first sinker region having a second conductivity type, a third length, a third width, and a third depth equal to or greater than the first depth, such that the first sinker region extends through the second sinker region or the well region; A step of forming a mask having at least one opening over the source region over the semiconductor substrate; A step of forming at least one trench having a fourth length and a fourth width defined by at least one opening within the active region through the at least one opening—the at least one trench having a fourth depth greater than the second depth such that the at least one trench extends through the source region—; and A method for forming a transistor element, comprising the step of forming an electrically conductive material within the at least one trench that is electrically coupled to the source region, the well region, and the first sinker region.

Description

Silicon Carbide Transistor with Interrupted Source Contacts Cross-reference of other applications This application claims priority to U.S. Provisional Patent Application No. 63/715,453, filed November 1, 2024, titled “Silicone Carbide Transistor with Uninterrupted Source Contacts,” the entirety of which is incorporated herein by reference for all purposes. Technology field The disclosed embodiments generally relate to transistor elements. More specifically, the disclosed embodiments relate to silicon carbide-based transistor elements. In the description below, various embodiments will be described. For the purpose of explanation, specific configurations and details are presented to provide a thorough understanding of the embodiments. However, it will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring the embodiments being described. A specific embodiment of the present application relates to a silicon carbide (SiC)-based transistor device. The transistor device comprises a plurality of transistor regions arranged as "stripe" spaced apart by a pitch that may be constant and distributed across an active region of a SiC substrate. Each stripe comprises a P-type doping region located adjacent to a JFET region. An N-type doping "source" region is formed within each P-type doping region. A plurality of source contact regions are formed within each N-type doping region and are separated by contact spacing that may be varied to achieve a desired stable resistance for the transistor device. Each source contact region is filled with an electrically conductive material (e.g., source metal) that forms electrical contact with the N-type doping region along the sidewall of each source contact region. Each source region also forms electrical contact with the P-type doping region along the bottom surface of the source contact region. Each P-type doping region includes a deep implant region having a perimeter defined by a mask placed on the upper surface of the substrate such that changing the perimeter (e.g., width) of the P-type doping region does not change the pitch of the transistor. For example, since the width of the deep implant region is not determined by the width of the P-type doping region or the N-type doping region, the width of the deep implant region can be increased without increasing the device pitch. The upper region of the transistor includes a source metal layer that is electrically isolated from the lower substrate by an interlayer dielectric, except when the source metal penetrates the interlayer dielectric to fill the source contact region. For example, a transistor element comprises a substrate having an upper surface and an active region having a first conductivity type. At least one transistor region is disposed within the active region, and each of the at least one transistor region comprises a well region, a source region, trenches, and a source electrode or conductor. The well region has a second conductivity type and a first depth from the upper surface, and the source region is disposed within the well region, has a first conductivity type, and has a second depth from the upper surface that is smaller than the first depth. The trenches are spaced apart (e.g., "interrupted") and extend from the upper surface through the source into the well region, and each trench includes at least one sidewall. And, a source conductor is disposed within each trench and is conductively in contact with the source region and the well region or electrically coupled thereto at one or more of the at least one sidewall. Several exemplary embodiments will now be described with respect to the accompanying drawings, which form part of this invention. The following description is intended merely to provide the embodiment(s) and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the following description of the embodiment(s) will provide those skilled in the art with a practicable description for implementing one or more embodiments. It is understood that various changes may be made to the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are provided for the purpose of explanation and to provide a complete understanding of a particular creative embodiment. However, it will be apparent that various embodiments may be practiced without these specific details. The drawings and description are not intended to be limiting. The words “example” or “exemplary” are used herein to mean “serving as an example, case, or example.” Any embodiment or design described herein as “exemplary” or “example” should not be interpreted as being preferred or advantageous over other embodiments or designs. FIG. 1a is an isometric cross-sectional view of a transistor e