KR-20260065654-A - SEMICONDUCTOR DEVICE

Abstract

Embodiments according to the present disclosure may provide a semiconductor device with improved electrical characteristics and reliability. The semiconductor device comprises a first semiconductor substrate on which a first semiconductor element is disposed and a second semiconductor substrate on which a second semiconductor element is disposed. A bonding region between the first semiconductor element and the second semiconductor element comprises a first region, a second region, and a third region disposed between the first region and the second region and surrounding the first region. The bonding region comprises at least one first bonding pad disposed in the first region, at least one second bonding pad disposed in the second region, and at least one third bonding pad disposed in the third region. The third bonding pad may surround at least one first bonding pad.

Inventors

• 정재호
• 최봉현

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260511

Application Date

20241101

Claims (10)

1. A first semiconductor substrate having a first semiconductor device disposed thereon; and A second semiconductor substrate having a second semiconductor device disposed thereon Includes, The bonding region between the first semiconductor device and the second semiconductor device comprises a first region, a second region, and a third region disposed between the first region and the second region and surrounding the first region. The bonding area above is, At least one first bonding pad disposed in the first area above; At least one second bonding pad disposed in the second area; and At least one third bonding pad disposed in the third area above Includes, A semiconductor device in which the third bonding pad surrounds the at least one first bonding pad.
2. In Article 1, A semiconductor device in which the third region surrounds the first region in a closed curve shape in a horizontal direction parallel to the front surface of the first semiconductor device or the front surface of the second semiconductor device.
3. In Article 2, A semiconductor device in which the third bonding pad extends in a line shape along the third region and surrounds the first region by forming a closed curve in the horizontal direction.
4. In Article 1, The above at least one first bonding pad is formed by bonding a first lower bonding pad disposed on the first semiconductor device in the first region and a first upper bonding pad disposed on the second semiconductor device, and The above at least one second bonding pad is formed by bonding a second lower bonding pad disposed on the first semiconductor device in the second region and a second upper bonding pad disposed on the second semiconductor device, and The above at least one third bonding pad is formed by bonding a third lower bonding pad disposed on the first semiconductor device in the third region and a third upper bonding pad disposed on the second semiconductor device. Semiconductor device.
5. In Article 1, A semiconductor device in which the first bonding pad is electrically connected to at least one of the first semiconductor device and the second semiconductor device.
6. In Article 1, A semiconductor device in which the third bonding pad extends in a line shape along the third region, and the line width of the third bonding pad in the line shape is smaller than or equal to the width of the first bonding pad.
7. Substrate; Peripheral circuit structure disposed on the above substrate; A cell structure disposed on the above peripheral circuit structure; and A bonding region comprising at least one first bonding pad, at least one second bonding pad, and at least one third bonding pad disposed between the peripheral circuit structure and the cell structure. Includes, The above at least one first bonding pad is disposed in a first area of the bonding area, and The above at least one second bonding pad is disposed in a second area of the bonding area, and The above at least one third bonding pad is disposed in the third region of the bonding area, and The third region is positioned between the first region and the second region and surrounds the first region, and The third bonding pad above surrounds the at least one first bonding pad, Semiconductor device.
8. In Article 7, The above cell structure is, A mold structure comprising a plurality of gate electrodes and a mold insulating layer surrounding the plurality of gate electrodes; A plurality of channel structures formed to penetrate the above mold structure in a vertical direction; It includes a plurality of word line structures connected to each of the plurality of gate electrodes, and A semiconductor device in which the above vertical direction is a direction perpendicular to the upper surface of the substrate.
9. In Article 7, A semiconductor device in which the third region surrounds the first region in a closed curve shape in a horizontal direction parallel to the upper surface of the substrate.
10. A first semiconductor substrate having a first semiconductor device disposed thereon; and A second semiconductor substrate having a second semiconductor device disposed thereon Includes, The bonding region between the first semiconductor device and the second semiconductor device comprises a first region, a second region, and a third region disposed between the first region and the second region and surrounding the first region. The bonding area above is, A first bonding pad disposed in the first region, wherein the first lower bonding pad disposed on the first semiconductor device in the first region and the first upper bonding pad disposed on the second semiconductor device are bonded to form the first bonding pad; A second bonding pad disposed in the second region, wherein the second lower bonding pad disposed on the first semiconductor device in the second region and the second upper bonding pad disposed on the second semiconductor device are bonded to form the second bonding pad; and A third bonding pad disposed in the third region, wherein the third lower bonding pad disposed on the first semiconductor device in the third region and the third upper bonding pad disposed on the second semiconductor device are bonded to form the third bonding pad. Includes, The third region surrounds the first region in a closed curve shape in a horizontal direction parallel to the front surface of the first semiconductor device or the front surface of the second semiconductor device, and The third bonding pad extends in a line shape along the third region and surrounds the first region by forming a closed curve in the horizontal direction. Semiconductor device.

Description

Semiconductor Device The present disclosure relates to a semiconductor device. Semiconductor devices are core components used to control or amplify electrical signals in electronic devices, and various types of semiconductor devices can be manufactured. For example, memory devices are primarily used to store and retrieve data, while non-memory devices are used to control or amplify electrical signals. As key elements of electronic devices, semiconductor devices play an important role in diverse fields, including computers, communication equipment, and consumer electronics. To improve the integration density of semiconductor devices, a process of joining two or more wafers using hybrid bonding technology is being utilized. However, since defects occur during this wafer joining process due to reasons such as particles remaining between the wafers, measures to ensure the reliability of semiconductor devices are required. FIG. 1 is a plan view for illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a plan view illustrating a portion of a chip area according to some embodiments of the present disclosure. FIG. 3 is an example of a cross-sectional view taken along the line AA' of FIG. 1. FIG. 4 is an example of a cross-sectional view taken along the line AA' of FIG. 1. FIG. 5 is an example of a cross-sectional view taken along the CC' line of FIG. 1. FIG. 6a is an example of a cross-sectional view taken along the BB' line of FIG. 1. FIG. 6b is an example of a cross-sectional view taken along the line BB' of FIG. 1. FIG. 7 is an example of a cross-sectional view taken along the BB' line of FIG. 1. FIGS. 8 to 11 are drawings for explaining a method for manufacturing a third bonding pad according to one embodiment of the present disclosure. FIG. 12 is a drawing showing a part of a semiconductor device having a third bonding pad formed thereon according to one embodiment of the present disclosure. FIG. 13 is a drawing for illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 14 is an exemplary block diagram for illustrating an electronic system according to some embodiments of the present disclosure. A semiconductor device according to some embodiments of the present disclosure will be described in detail below with reference to the drawings. In the following description, a semiconductor device may refer to a semiconductor wafer, a semiconductor chip, etc., including an integrated circuit that performs a specific function. Two or more semiconductor chips may be connected using bonding pads. Here, the bonding pads may include an active bonding pad that performs a bonding function while being electrically connected to the integrated circuit, and a dummy bonding pad that performs only a bonding function without being electrically connected to other components. FIG. 1 is a plan view for illustrating a semiconductor device (10) according to some embodiments of the present disclosure. FIG. 2 is a plan view for illustrating a portion of a chip region (CR) according to some embodiments of the present disclosure. FIG. 3 is an example of a cross-sectional view cut along the line A-A' of FIG. 1. FIG. 4 is an example of a cross-sectional view cut along the line A-A' of FIG. 1. FIG. 5 is an example of a cross-sectional view cut along the line C-C' of FIG. 1. FIG. 6a is an example of a cross-sectional view cut along the line B-B' of FIG. 1. FIG. 6b is an example of a cross-sectional view cut along the line B-B' of FIG. 1. FIG. 7 is an example of a cross-sectional view cut along the line B-B' of FIG. 1. Referring to FIGS. 1 and 2, a semiconductor device (10) according to some embodiments of the present disclosure may be formed by bonding a first semiconductor chip (100) and a second semiconductor chip (200) and may include a chip region (CR) and an edge region (ER). The chip region (CR) may be a high-density region with a relatively high pattern density, and the edge region (ER) may be a low-density region with a relatively low pattern density or no patterns. The chip region (CR) may include a cell array region of a semiconductor memory device, a peripheral circuit region including circuits configured to be electrically connected to the cell arrays included in the cell array region, and a core region. In some embodiments, the chip region (CR) may include a memory device. However, the chip region (CR) may include a non-memory device, but is not limited thereto. The edge region (ER) may refer to an area configured to include a portion that is scribed or cut when dividing a plurality of chip regions (CR) into individual chip regions (CR). The edge region (ER) may also be referred to as a scribe lane, scribe line, outer region, outer region, or cutting region. The edge region (ER) may be located at the edge of the chip region (CR) to form the boundary of the chip region (CR). In some embodiments, the chip region (CR) may include at least one n