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KR-20260065671-A - SEMICONDUCTOR PACKAGE

KR20260065671AKR 20260065671 AKR20260065671 AKR 20260065671AKR-20260065671-A

Abstract

A redistribution structure of a semiconductor package according to an embodiment comprises redistribution lines of the redistribution structure and test pads and test wiring lines for testing electrical reliability regarding electrical openness and/or electrical shorting to a bridge chip. Through this, the embodiment can test whether normal electrical signals are transmitted through the redistribution lines and the bridge chip. For example, the embodiment can test whether there is electrical openness and/or electrical shorting of the redistribution lines and the bridge chip. Through this, the embodiment can minimize losses caused by product defects occurring during the manufacturing process of the semiconductor package. Furthermore, the embodiment can facilitate the electrical reliability testing of the redistribution structure of the semiconductor package.

Inventors

  • 김수윤
  • 이정원
  • 강인수

Assignees

  • 주식회사 네패스

Dates

Publication Date
20260511
Application Date
20241101

Claims (12)

  1. Bridge chip; A rewiring structure disposed on the above bridge chip; and It includes a plurality of semiconductor chips disposed on the above-mentioned redistribution structure and spaced apart from each other along the horizontal direction, The above-described redistribution structure comprises a redistribution insulating layer, a redistribution line disposed within the redistribution insulating layer, and a redistribution pad disposed on the redistribution insulating layer. The above redistribution line includes a first redistribution line electrically connected to the bridge chip and the plurality of semiconductor chips, and The above-mentioned rewiring pad includes a first signal pad that electrically connects the first rewiring line and the terminal pads of the plurality of semiconductor chips, and a first test pad spaced apart along a horizontal direction from the first signal pad. A semiconductor package, wherein the above-described rewiring structure further includes a first test wiring line that electrically connects the first test pad and the first rewiring line.
  2. In paragraph 1, The first redistribution line comprises a first part including a redistribution pattern arranged at a first vertical level, and a second part including a redistribution pattern arranged at a second vertical level different from the first vertical level. A semiconductor package having a plurality of first test pads and first test wiring lines, each connected to the first part and the second part of the first rewiring line, respectively.
  3. In paragraph 1, The above redistribution line further includes a second redistribution line electrically connected to a terminal pad of at least one semiconductor chip among the plurality of semiconductor chips and not electrically connected to the bridge chip, and a third redistribution line electrically connected to a terminal pad of at least one other semiconductor chip among the plurality of chips and not electrically connected to the bridge chip. The above-mentioned rewiring pad includes a second signal pad that electrically connects the second rewiring line and a terminal pad of at least one of the plurality of semiconductor chips, a second test pad spaced apart along a horizontal direction from the second signal pad, a third signal pad that electrically connects the third rewiring line and a terminal pad of at least one of the plurality of semiconductor chips, and a third test pad spaced apart along a horizontal direction from the third signal pad. A semiconductor package, wherein the above-described rewiring structure further comprises a second test wiring line electrically connecting the second test pad and the second rewiring line, and a third test wiring line electrically connecting the third test pad and the third rewiring line.
  4. In any one of paragraphs 1 through 3, A semiconductor package in which at least one of the width in the horizontal direction of the first signal pad and the planar shape of the first signal pad is different from at least one of the width in the horizontal direction of the first test pad and the planar shape of the first test pad.
  5. In any one of paragraphs 1 through 3, It further includes conductive bumps disposed between the above-mentioned rewiring pad and the plurality of semiconductor chips, and A semiconductor package comprising a conductive bump, the first bump disposed between the first signal pad and the terminal pad of at least one of the plurality of semiconductor chips, and a second bump disposed between the first test pad and the dummy terminal of at least one of the plurality of semiconductor chips.
  6. In any one of paragraphs 1 through 3, It further includes an underfill member disposed between the above-mentioned redistribution structure and the plurality of semiconductor chips, and The upper surface of the first test pad is provided with a concave recess facing the lower surface of the first test pad, and The above underfill member fills the above recess and is provided in a semiconductor package.
  7. In paragraph 6, A first molding member positioned to surround the sidewall of the bridge chip; A second molding member disposed to surround the sidewall of the underfill member and the sidewall of the plurality of semiconductor chips; and A semiconductor package further comprising a vertical connection conductor that penetrates the first molding member along a vertical direction and is electrically connected to the redistribution structure.
  8. In any one of paragraphs 1 through 3, The above-mentioned rewiring structure includes an effective area located inside the sawing line and a dummy area around the perimeter of the effective area located outside the sawing line, The above first test pad is placed in the above dummy area, and A semiconductor package, wherein a portion of the first test wiring line is placed in the dummy area and the remainder of the first test wiring line is placed in the effective area.
  9. In any one of paragraphs 1 through 3, The bridge chip comprises a bridge insulating layer, a bridge wiring line disposed within the bridge insulating layer, and a connection pad disposed on the bridge insulating layer. A semiconductor package comprising a signal connection pad that is electrically connected to the first rewiring line and the terminal pads of the plurality of semiconductor chips.
  10. In Paragraph 9, The above connection pad further includes a test connection pad that is spaced apart along the horizontal direction from the signal connection pad and is electrically connected to the first test wiring line, and A semiconductor package comprising a bridge chip that further includes a test connection wiring line electrically connecting the test connection pad and the bridge wiring line.
  11. In Paragraph 9, The bridge chip further includes a temperature sensing unit comprising an electrode layer disposed within the bridge insulating layer and an electrode pad disposed on the bridge insulating layer and connected to the electrode layer. The above temperature sensing unit is a semiconductor package electrically connected to the above redistribution structure.
  12. In paragraph 2, The above-mentioned redistribution structure further includes a redistribution pattern arranged at the first vertical level and a dummy pattern spaced apart along the horizontal direction, and A semiconductor package in which the above dummy pattern overlaps with at least one rewiring via along the vertical direction.

Description

Semiconductor Package The embodiment relates to a semiconductor package, and in particular to a semiconductor package capable of verifying the electrical reliability of the wirings and a method for manufacturing the same. Due to the increasing performance of various mobile devices, the number of input/output (I/O) terminals required in semiconductors is growing. Accordingly, Wafer Level Packaging (WLP) technology, which performs semiconductor packaging processes at the wafer level and separates the wafer-level semiconductor packages into individual units, is gaining attention. Fan-Out Wafer Level Package (FOWLP) or Fan-Out Panel Level Package (FOPLP) is a technology that mounts semiconductor chips directly onto a wafer rather than on a circuit board (e.g., a PCB). For semiconductor packages manufactured using FOWLP and/or FOPLP, manufacturing costs can be lowered by eliminating the need for a circuit board, and it enables package miniaturization, improved heat dissipation, reduced power consumption, and enhanced frequency bandwidth. FOWLP or FOPLP is manufactured by attaching individual dies to a carrier, molding them with a molding member, and subsequently performing processes such as forming a fan-out type redistribution layer (RDL) and bumping. At this time, the process of manufacturing a semiconductor package according to FOWLP or FOPLP as described above includes a first process of attaching a bridge chip on a carrier member, a second process of forming a redistribution structure on the bridge chip, and a third process of mounting a plurality of semiconductor devices on the redistribution structure. At this time, the first to third processes of the semiconductor package described above may be carried out by stacking different materials along the vertical direction. For example, the redistribution insulating layer of the redistribution structure may include an organic material, the die may include silicon, and the molding member may include EMC (Epoxy Mold Compound). Furthermore, these may have different physical properties (e.g., coefficient of thermal expansion). Additionally, each of the above materials undergoes a curing process after stacking. At this time, warping of the semiconductor package may occur during the curing process. For example, the semiconductor package has a problem in which convex warping toward the upward direction (crying warpage) or concave warping toward the downward direction (smile warpage) occurs due to different coefficients of thermal expansion between the materials described above during the manufacturing process, and/or shrinkage or expansion during the curing process. In addition, if bending as described above occurs, processability in the process of forming the redistribution structure may be reduced, which may complicate the manufacturing process and lower the product yield. Furthermore, problems may arise regarding reduced electrical reliability between the redistribution structure, the bridge chip, and the semiconductor device. For example, a problem may occur where the signal line between the redistribution structure and the bridge chip becomes electrically open. At this time, if a defect resulting from an electrical open circuit as described above occurs while the semiconductor device is mounted, the mounted semiconductor device is also treated as defective, leading to a problem of increased manufacturing costs. In particular, the aforementioned semiconductor device is quite expensive, and consequently, if the semiconductor device is treated as defective, there is a problem of significantly increased wasted costs. Accordingly, there is a need for technology that can efficiently perform electrical verification of wirings before semiconductor devices are mounted, and furthermore, solve the problem of reduced electrical reliability caused by damage to wirings during the verification process. FIG. 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. Figure 2 is an enlarged plan view of one area (R1) of Figure 1. Figure 3 is a drawing to explain a modified example of the signal pad and test pad of the rewiring structure of Figure 2. FIG. 4 is a cross-sectional view showing a semiconductor package according to a second embodiment. FIGS. 5a to 5h are cross-sectional views for explaining the manufacturing method of a semiconductor package illustrated in FIG. 4 in process order. FIG. 6 is a cross-sectional view showing a semiconductor package according to a third embodiment. FIG. 7 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. Figure 8 is a plan view illustrating the semiconductor package of Figure 7. FIG. 9 is a cross-sectional view showing a semiconductor package according to the fifth embodiment. FIG. 10 is a cross-sectional view showing the bridge chip of FIG. 9 in detail. FIG. 11 is a plan view showing the signal connection pad and test connection pad provided on the bridge chip of F