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KR-20260065686-A - semiconductor package and manufacturing method the same

KR20260065686AKR 20260065686 AKR20260065686 AKR 20260065686AKR-20260065686-A

Abstract

A method for manufacturing a semiconductor package according to the present invention may include attaching a first surface of a via structure including an opening on an upper surface of an adhesive member; forming conductive connections and a bridge chip on the upper surface of the adhesive member and within the opening; removing the adhesive member; forming a first redistribution substrate on the first surface of the via structure; mounting chip structures on the first redistribution substrate; and forming a second redistribution substrate on a second surface facing the first surface of the via structure in a vertical direction. The bridge chip includes a first surface and a second surface facing each other in the vertical direction, and the first surface of the bridge chip and the first surface of the via structure may be located at different levels.

Inventors

  • 최대연
  • 고태호
  • 강운병
  • 박석봉

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260511
Application Date
20241101

Claims (10)

  1. Attaching a first surface of a via structure including an opening on the upper surface of an adhesive member; Forming conductive connections and a bridge chip on the upper surface of the adhesive member and within the opening; Removing the above adhesive member; Forming a first redistribution substrate on the first surface of the above via structure; Mounting chip structures on the first redistribution board; and The method comprises forming a second redistribution substrate on a second surface facing perpendicularly to the first surface of the via structure, wherein The above bridge chip includes a first surface and a second surface facing each other in the vertical direction, and A method for manufacturing a semiconductor package in which the first surface of the bridge chip and the first surface of the via structure are located at different levels.
  2. In claim 1, A method for manufacturing a semiconductor package comprising a via structure, a via base layer, and conductive posts penetrating the via base layer.
  3. In claim 2, A method for manufacturing a semiconductor package in which the via base layer comprises at least one of silicon, glass, or organic material.
  4. In claim 2, A method for manufacturing a semiconductor package comprising at least one of fiber glass epoxy, glass paper epoxy, Teflon, resin coated copper (RCC), or ceramic.
  5. In claim 2, The above challenge posts have heights measured in the above vertical direction, A method for manufacturing a semiconductor package in which the dispersion of the above heights is less than 10 μm.
  6. In claim 5, A method for manufacturing a semiconductor package in which the heights of the challenge posts are 100 to 250 μm.
  7. In claim 2, The above-mentioned challenge posts are spaced apart from each other in a first direction and a second direction that are parallel to and intersect the first surface of the above-mentioned via structure, and A method for manufacturing a semiconductor package in which the first distance along the first direction of the conductive posts adjacent to each other in the first direction is 0.8 to 1.2 times the diameter of the conductive posts.
  8. In claim 7, A method for manufacturing a semiconductor package in which the second distance along the second direction of the challenge posts adjacent to each other in the second direction is 0.8 to 1.2 times the diameter of the challenge posts.
  9. In claim 1, After forming the above conductive connections and the bridge chip, A method for manufacturing a semiconductor package further comprising forming a bridge mold film covering the conductive connections and the bridge chip on the upper surface of the adhesive member and within the opening.
  10. In claim 1, A method for manufacturing a semiconductor package further comprising forming a first carrier substrate on the second surface of the via structure after forming the conductive connection portions and the bridge chip, and before removing the adhesive member.

Description

Semiconductor package and manufacturing method the same The present invention relates to a semiconductor package, and more specifically, to a semiconductor package including a redistribution substrate and a method for manufacturing the same. With the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. In response to this trend, recent packaging technology is moving toward integrating multiple semiconductor chips within a single package. A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting the semiconductor chip onto a printed circuit board (PCB) and electrically connecting them using bonding wires or bumps. With the recent advancement of the electronics industry, semiconductor packages are evolving in various directions with the goals of miniaturization, weight reduction, and manufacturing cost reduction. Furthermore, as their applications expand to include high-capacity storage devices, a wide variety of semiconductor packages are emerging. FIG. 1 is a plan view of a semiconductor package according to some embodiments of the present invention. Figure 2a is a cross-sectional view along the line A-A' of Figure 1. FIG. 2b is a plan view of a via structure (100) according to some embodiment of the present invention. Figure 2c is an enlarged view of part C of Figure 2a. Figure 2d is an enlarged view of part D of Figure 2a. FIGS. 3 to 14 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to some embodiments of the invention, specifically cross-sectional views corresponding to line A-A' of FIG. 1. FIG. 15 is a cross-sectional view of a semiconductor package according to some embodiment of the present invention. The present invention will be described in detail below by explaining embodiments of the present invention with reference to the attached drawings. FIG. 1 is a plan view of a semiconductor package according to some embodiments of the present invention. FIG. 2a is a cross-sectional view along line A-A' of FIG. 1. FIG. 2b is a plan view of a via structure (100) according to some embodiments of the present invention.FIG. 2c is an enlarged view of part C of FIG. 2a. FIG. 2d is an enlarged view of part D of FIG. 2a. Referring to FIGS. 1 and FIGS. 2a through 2d, a semiconductor package (10) according to an embodiment of the present invention may include a first redistribution substrate (200), a second redistribution substrate (300), a via structure (100), a bridge chip (150), and chip structures (400, 600). The chip structures (400, 600) may, for example, include a unit chip package (400) and a base chip (600). The second redistribution substrate (300) may have a first surface (300a) and a second surface (300b) facing each other in a third direction (D3). In the description of FIGS. 1 and FIGS. 2a through 2d, the first direction (D1) and the second direction (D2) may be directions parallel to the first surface (300a) of the second redistribution substrate (300) and intersecting each other. The third direction (D3) may be a vertical direction (D3) perpendicular to the first surface (300a) of the second redistribution board (300). The third direction (D3) may also be referred to as a vertical direction (D3). For example, the first to third directions (D1, D2, D3) may be directions orthogonal to each other. The unit chip package (400) and the base chip (600) may be spaced apart from each other in horizontal directions (D1, D2). For example, the unit chip package (400) and the base chip (600) may be spaced apart from each other in a first direction (D1). The unit chip package (400) and the base chip (600) may have a chiplet structure. A chiplet may mean dividing existing chips by function to form separate chips, and then connecting the chips with a connecting structure. The second redistribution board (300) may include a plurality of second redistribution insulating layers (310), second redistribution patterns (320), and redistribution connection terminals (350) stacked in the vertical direction (D3). The second redistribution insulating layers (310) may include an organic material, for example, a photo-imageable dielectric (PID). The photo-imageable dielectric may be a polymer. The photo-imageable dielectric may include, for example, at least one of a photosensitive polyimide, polybenzoxazole, a phenolic polymer, and a benzocyclobutene polymer. Although the boundary between the second redistribution insulating layers (310) is shown in FIG. 2a, the invention is not limited thereto. According to other embodiments, the interface between adjacent second redistribution insulating layers (310) may not be distinguishable. A second redistribution pattern (320) may be disposed within the second redistribution insulating layers (310). The second redistribution patt