KR-20260065729-A - SEMICONDUCTOR PACKAGE AND A METHOD FOR FORMING THE SAME

KR20260065729AKR 20260065729 AKR20260065729 AKR 20260065729AKR-20260065729-A

Abstract

A method for forming a semiconductor package comprises: providing a molded interposer module, wherein the molded interposer module comprises an interposer having at least one central opening and a chip mounting area surrounding at least one central opening, a plurality of semiconductor chips mounted on the chip mounting area, and a mold cap formed on the chip mounting area of the interposer to encapsulate the plurality of semiconductor chips; placing the molded interposer module on a substrate through solder paste, wherein a flux material is formed around the solder paste, and the molded interposer module and the substrate together form a space for receiving the solder paste, and the space has a side slit communicating with an external environment; reflowing the solder paste to form a solder bump; and spraying a deflux chemical mist toward the solder bump through at least one central opening and the side slit.

Inventors

이, 지선
맹, 범렬
안, 예지

Assignees

스태츠 칩팩 매니지먼트 피티이. 엘티디.

Dates

Publication Date: 20260511
Application Date: 20251029
Priority Date: 20241101

Claims (14)

As a method for forming a semiconductor package, A step of providing a molded interposer module, wherein the molded interposer module comprises an interposer having at least one central opening passing through it and a chip mounting area surrounding the at least one central opening, a plurality of semiconductor chips mounted on the chip mounting area of the interposer, and a mold cap formed on the chip mounting area of the interposer to encapsulate the plurality of semiconductor chips; A step of placing the molded interposer module on a substrate using solder paste, wherein a flux material is formed around the solder paste, the molded interposer module and the substrate together form a space for receiving the solder paste, and the space has a side slit that fluidly communicates the space with an external environment; A step of reflowing the solder paste to form a plurality of solder bumps; and A method comprising the step of spraying a deflux chemical mist toward the plurality of solder bumps through at least one central opening and the side slits of the interposer.
In claim 1, the step of providing the molded interposer module is: A step of mounting the plurality of semiconductor chips on the chip mounting area of the interposer; A step of forming the mold cap on the interposer to encapsulate the plurality of semiconductor chips; A step of attaching the above mold cap onto a carrier; A step of etching through the interposer and the mold cap to form at least one central opening, thereby forming the molded mold interposer module; and A method comprising the step of removing the molded interposer module from the carrier.
In claim 1, the step of placing the interposer module formed on the substrate is: A step of forming the solder paste on at least one of the substrate and the molded interposer module; A step of forming the flux material around the solder paste; and A method comprising the step of attaching the molded interposer module on the substrate through the plurality of solder bumps.
In claim 1, after the step of placing an interposer module formed on the substrate, the method is: A method further comprising the step of attaching additional electronic devices directly onto the substrate around the molded interposer module.
In paragraph 4, after the step of spraying a deflux chemical mist toward the plurality of solder bumps, the method is: A method further comprising the step of forming the mold on the substrate to encapsulate the molded interposer module and the additional electronic device.
In claim 1, after the step of spraying a deflux chemical mist toward the plurality of solder bumps, the method comprises: A method further comprising the step of filling at least one central opening of the interposer by distribution.
As a semiconductor package, Substrate; An interposer mounted on the substrate and having at least one central opening passing through it and a chip mounting area surrounding the at least one central opening; and A semiconductor package comprising a plurality of semiconductor chips mounted on a chip mounting area of the interposer.
In Paragraph 7, A semiconductor package further comprising a mold cap formed on a chip mounting area of the interposer to encapsulate the plurality of semiconductor chips.
In claim 8, the mold cap is also formed within the at least one central opening and between the plurality of semiconductor chips, forming a semiconductor package.
In claim 7, the semiconductor package, wherein the substrate has at least one slot passing through it and connected to at least one central opening.
A semiconductor package according to claim 7, wherein the plurality of semiconductor chips comprises at least three semiconductor chips, and each of the at least one central opening is aligned with the gap between two of the plurality of semiconductor chips.
A semiconductor package according to claim 7, further comprising a plurality of solder bumps disposed between the interposer and the substrate and providing an electrical connection therebetween.
A semiconductor package according to claim 12, further comprising an underfill material formed between each of the interposer, the substrate, and the plurality of solder bumps.
As a method for forming a semiconductor package, A step of providing an unmolded interposer module, wherein the unmolded interposer module comprises an interposer having at least one central opening passing through it and a chip mounting area surrounding the at least one central opening, and a plurality of semiconductor chips mounted on the chip mounting area of the interposer; A step of placing the unmolded interposer module on a substrate through a solder paste, wherein a flux material is formed around the solder paste, the unmolded interposer module and the substrate together form a space for receiving the solder paste, and the space has a side slit that fluidly communicates the space with an external environment; A step of reflowing the solder paste to form a plurality of solder bumps; and A method comprising the step of spraying a deflux chemical mist toward the plurality of solder bumps through at least one central opening and the side slits of the interposer.

Description

Semiconductor Package and Method for Forming the Same The present application relates to semiconductor technology in general, and more specifically, to a semiconductor package and a method for forming a semiconductor package. The semiconductor industry continues to face complex integration challenges as consumers demand that their electronic devices be smaller, faster, and higher-performing, with more functions packed into a single device. In some semiconductor packages, Package-in-Package (PiP) or Package-on-Package (PoP) processes are used to combine two or more integrated circuit (IC) packages into a single integrated device. PiP or PoP devices can utilize space more efficiently and reduce the length of signal paths between packages. In a typical PiP or PoP device, one or more pre-formed semiconductor packages or semiconductor chips can be mounted onto other semiconductor packages or substrates via an interposer or other similar structure. However, it is noted that the number of semiconductor chips required to be mounted on a substrate increases significantly, and the deployment of these semiconductor chips on the substrate is primarily determined by the size of the interposer. However, in the case of Chip on Wafer (CoW) packages, also referred to as molded interposers, several process problems exist due to the large size of the interposer. One of these is that after a large CoW package (e.g., 30 mm x 30 mm or larger) is attached to a substrate via solder bumps, deflux chemicals cannot penetrate through the CoW package, leaving flux residue between the CoW package and the substrate. Flux residue can degrade the performance and reliability of the device. Therefore, there is a need for further improvements to semiconductor packages or devices having large CoWs or similar large-scale components. The drawings referenced herein form a part of the specification. The features illustrated in the drawings illustrate only some embodiments of the present application, and not all embodiments of the present application, unless expressly otherwise indicated in the detailed description, and readers of the specification should not imply otherwise. FIGS. 1a to 1f are drawings illustrating a method for forming a semiconductor package according to an embodiment of the present application. FIG. 1g is a drawing illustrating an exemplary layout of a semiconductor chip on an interposer of a semiconductor package shown in FIG. 1a. FIG. 1h is a drawing illustrating an exemplary layout of a semiconductor chip on an interposer of a semiconductor package shown in FIG. 1d. FIG. 2 is a drawing illustrating a semiconductor package according to an embodiment of the present application. FIG. 3 is a drawing illustrating a semiconductor package according to an embodiment of the present application. FIG. 4 is a drawing illustrating a semiconductor package according to an embodiment of the present application. FIG. 5 is a drawing illustrating a semiconductor package according to an embodiment of the present application. FIG. 6a is a drawing illustrating a semiconductor package according to an embodiment of the present application. FIG. 6b is a drawing illustrating an exemplary layout of a semiconductor chip on an interposer of a semiconductor package shown in FIG. 6a. The same reference number will be used to refer to identical or similar parts throughout the drawing. The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings, which form part of the description. The drawings illustrate specific exemplary embodiments in which the present application may be practiced. Including the drawings, the detailed description describes these embodiments in sufficient detail to enable a person skilled in the art to practice the present application. A person skilled in the art may further utilize other embodiments of the present application and may make logical, mechanical, and other modifications without departing from the spirit or scope of the present application. Accordingly, readers of the following detailed description should not interpret the description as limiting, and only the appended claims define the scope of the embodiments of the present application. In this application, the use of the singular form includes the plural form unless specifically otherwise specified. In this application, the use of "or" means "and/or" unless otherwise specified. Furthermore, the use of the term "comprising" as well as other forms such as "comprising" and "included" is not limiting. Additionally, terms such as "element" or "component" include all elements and components comprising one unit and all elements and components comprising more than one subunit, unless specifically otherwise specified. Furthermore, section headings used in this specification are for organization purposes only and should not be interpreted as limiting the described subject matter. As used herein, spatial relative terms suc