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KR-20260065741-A - Semiconductor structure and method for manufacturing the semiconductor structure

KR20260065741AKR 20260065741 AKR20260065741 AKR 20260065741AKR-20260065741-A

Abstract

As a semiconductor structure and a method for forming a semiconductor structure, the semiconductor structure comprises at least a substrate, a bit line structure, a first dielectric layer, a contact structure, and a conductive structure, wherein the bit line structure is located on the substrate, and a plurality of bit line structures are extended along a first direction and spaced apart along a second direction, and the first direction is perpendicular to the second direction; the first dielectric layer is located between adjacent bit line structures and spaced apart along the first direction; the contact structure is located between adjacent bit line structures and the contact structure is spaced apart from the first dielectric layer; the conductive structure is located on top of the contact structure, and the uppermost part of the conductive structure and the uppermost part of the first dielectric layer are located on the same plane; and the contact structure gradually decreases in size from the uppermost part of the contact structure to the surface of the substrate along a direction perpendicular to the substrate.

Inventors

  • 주 순
  • 천 룽양
  • 스 롼
  • 팡 커
  • 천 인추
  • 쑨 야오
  • 리 광청

Assignees

  • 씨엑스엠티 코포레이션

Dates

Publication Date
20260511
Application Date
20250313
Priority Date
20241030

Claims (17)

  1. As a semiconductor structure, The above semiconductor structure is, It includes a substrate (10), a bit line structure (20), a first dielectric layer (60), a contact structure (70), and a conductive structure (80); The bit line structure is positioned on the substrate (10), and a plurality of the bit line structures (20) are extended along a first direction (X) and spaced apart along a second direction (Y), and the first direction (X) and the second direction (Y) are perpendicular; The first dielectric layer (60) is located between adjacent bit line structures (20) and is spaced apart along the first direction (X); The above contact structure (70) is located between adjacent bit line structures (20), and the above contact structure (70) is installed spaced apart from the first dielectric layer (60); The conductive structure (80) is located on the upper side of the contact structure (70), and the uppermost part of the conductive structure (80) is located in the same plane as the uppermost part of the first dielectric layer (60); The above contact structure (70) is a semiconductor structure characterized by the size of the contact structure (70) gradually decreasing from the uppermost part of the contact structure (70) to the surface of the substrate (10) along a direction perpendicular to the substrate (10).
  2. In paragraph 1, The above conductive structure (80) comprises a first conductive structure (801) and a second conductive structure (802), wherein the uppermost surface of the first conductive structure (801) and the first dielectric layer (60) is located on the same plane, the second conductive structure (802) is located between the first conductive structure (801) and the contact structure (70), and the conductive structure (80) is characterized by gradually increasing in size from the uppermost part to the bottom along a direction perpendicular to the substrate (10).
  3. In paragraph 1, A semiconductor structure characterized in that the contact area between the conductive structure (80) and the contact structure (70) is larger than the cross-sectional area of the conductive structure (80) at any one location and larger than the cross-sectional area of the contact structure (70) at any one location.
  4. In paragraph 1, The semiconductor structure further comprises an uppermost conductive structure (803), wherein the uppermost conductive structure (803) is located on the upper part of the conductive structure (80) and covers a portion of the uppermost surface of the first dielectric layer (60).
  5. In paragraph 1, A semiconductor structure characterized in that the size of the first dielectric layer (60) first decreases from the top to the bottom and then increases, and the first dielectric layer (60) is also provided with an air gap (90), and the air gap (90) is lower than the interface between the conductive structure (80) and the contact structure (70).
  6. In paragraph 1, The above contact structure (70) comprises a first contact structure (701) and a second contact structure (702), wherein the first contact structure (701) is inserted into the substrate (10), the second contact structure (702) is located at the top of the first contact structure (701), and the second contact structure (702) is characterized by gradually decreasing in size from the top to the bottom along a direction perpendicular to the substrate (10).
  7. As a method for forming a semiconductor structure, Step of providing a substrate (10); A step of forming a bit line structure (20) on the substrate (10) - the bit line structure (20) is extended along a first direction (X) and spaced apart along a second direction (Y), the first direction (X) and the second direction (Y) are perpendicular, and a first opening (301) is provided between adjacent bit line structures (20) - ; A step of forming a first conductive layer (401) in the first opening (301); A step of etching the first conductive layer (401) along a third direction (Z) to form a second opening (302), and using the remaining first conductive layer (401) as the second conductive layer (402) - the second conductive layer (402) and the second opening (302) are spaced apart along the first direction (X), and the third direction (Z) is perpendicular to the substrate (10) - ; A step of filling the first dielectric layer (60) into the second opening (302); A step of etching back the second conductive layer (402) to form a third opening (303) and using the remaining second conductive layer (402) as a contact structure (70); and The method includes the step of forming a conductive structure (80) in the third opening (303) - wherein the conductive structure (80) is located on the upper side of the contact structure (70); A method for forming a semiconductor structure characterized in that the contact structure (70) gradually decreases in size from the uppermost part of the contact structure (70) to the surface of the substrate (10) along a direction perpendicular to the substrate (10).
  8. In Paragraph 7, A method for forming a semiconductor structure, wherein the conductive structure (80) comprises a first conductive structure (801) and a second conductive structure (802), wherein the first conductive structure (801) is located in the third opening (303) and is located in the same plane as the uppermost surface of the first dielectric layer (60), the second conductive structure (802) is located between the first conductive structure (801) and the contact structure (70), and the size of the conductive structure (80) gradually increases from the uppermost part to the bottom along a direction perpendicular to the substrate (10).
  9. In Paragraph 7, A method for forming a semiconductor structure characterized in that the contact area between the conductive structure (80) and the contact structure (70) is larger than the cross-sectional area of the conductive structure (80) at any one location and larger than the cross-sectional area of the contact structure (70) at any one location.
  10. In Paragraph 7, A method for forming a semiconductor structure, wherein the semiconductor structure further includes an uppermost conductive structure (803), and the uppermost conductive structure (803) is located on the upper part of the conductive structure (80) and covers a portion of the upper surface of the first dielectric layer (60).
  11. In Paragraph 7, A method for forming a semiconductor structure characterized in that the size of the first dielectric layer (60) is first reduced from the top to the bottom and then increased; the first dielectric layer (60) is also provided with an air gap (90), and the air gap (90) is lower than the interface between the conductive structure (80) and the contact structure (70).
  12. In any one of paragraphs 7 through 11, A method for forming a semiconductor structure characterized in that the size of the second conductive layer (402) is first increased from the top to the bottom and then decreased, and the method for forming the second conductive layer (402) includes the step of using an oxidation process, an etching process, and a deoxidation process in a cyclic manner.
  13. In Paragraph 12, A method for forming a semiconductor structure characterized by performing the oxidation process using oxygen, wherein the bias of the oxidation process is gradually increased and the flow rate of the oxygen is gradually increased; wherein the etching gas of the etching process is at least one of chlorine and hydrogen bromide gas, the control gas of the etching process is oxygen, the flow rate of the etching gas is not changed, and the flow rate of the control gas is increased first and then decreased; wherein the deoxidation process removes by-products generated during the etching process through plasma, and the bias of the deoxidation process is gradually increased.
  14. In Paragraph 7, Prior to the step of forming the first conductive layer (401), the method of forming the semiconductor structure is, A method for forming a semiconductor structure, further comprising the step of etching the substrate (10) along the first opening (301) to form a first initial opening (301') - wherein the first conductive layer (401) is also filled into the first initial opening (301').
  15. In Paragraph 14, A method for forming a semiconductor structure, wherein the above contact structure (70) includes a first contact structure (701) and a second contact structure (702), wherein the first contact structure (701) is located at the first initial opening (301'), the second contact structure (702) is located at the top of the first contact structure (701), and the second contact structure (702) gradually decreases in size from the top to the bottom along a direction perpendicular to the substrate (10).
  16. In Paragraph 7, Prior to the step of etching the first conductive layer (401) along the third direction (Z) to form the second opening (302), the method of forming the semiconductor structure is: A method for forming a semiconductor structure, further comprising the steps of forming a film layer (50) stacked on the first conductive layer (401), etching the stacked film layer (50) to form a second initial opening (302'), and etching the first conductive layer (401) along the second initial opening (302') to form the second opening (302).
  17. In Paragraph 7, The step of filling the first dielectric layer (60) into the second opening (302) is specifically, A method for forming a semiconductor structure characterized by including the steps of filling a first initial dielectric layer (601) into the second opening (302), the first initial dielectric layer (601) also covering the surface of the second conductive layer (402), etching back the first initial dielectric layer (601) to form a fourth opening (304), forming a second initial dielectric layer (602) in the fourth opening (304), and the first initial dielectric layer (601) and the second initial dielectric layer (602) jointly constituting the first dielectric layer (60).

Description

Semiconductor structure and method for manufacturing the semiconductor structure The present application claims priority to a Chinese patent application filed on October 30, 2024, with application number 202411538538.8 and application title "Semiconductor structure and method for manufacturing a semiconductor structure," the entire contents of said Chinese patent application are incorporated into the present application by reference. Embodiments of the present invention relate to the field of semiconductors, and in particular to a method for manufacturing a semiconductor structure. In the manufacturing process of DRAM (Dynamic Random Access Memory), as chip sizes continue to shrink, process difficulties are becoming increasingly prominent, which can degrade the connection performance of conductive and contact structures and lead to problems such as short circuits between adjacent conductive structures or adjacent contact structures. One or more embodiments are described by way of example through photographs in the corresponding drawings, and such exemplary description does not constitute a limitation on the embodiments, and unless specifically stated otherwise, the attached drawings do not constitute a scale limitation; in order to explain the embodiments of the present invention or the technical methods of the prior art in more detail, a brief description of the drawings to be used for the embodiments is provided below, and the drawings described below are merely some embodiments of the present invention, and it is obvious that a person skilled in the art can obtain other drawings based on these drawings without requiring creative labor. FIG. 1 is a planar example of a semiconductor structure provided in an embodiment of the present invention. FIGS. 2 to 20 are process flow diagrams of a semiconductor structure formation method provided in one embodiment of the present invention, wherein FIGS. 2 to 5 are cross-sectional views along the BB' direction in FIG. 1, FIGS. 6 to 20 are cross-sectional views along the DD' direction in FIG. 1, and FIG. 17 is a planar example of FIG. 16. FIG. 21 is an exemplary diagram of a semiconductor structure provided in one embodiment of the present invention. FIG. 22 is an exemplary diagram of a semiconductor structure provided in another embodiment of the present invention. As can be seen from the background technology, in the manufacturing process of DRAM (Dynamic Random Access Memory), as chip size continues to shrink, process difficulties are becoming increasingly prominent, which can degrade the connection performance of conductive and contact structures and lead to problems such as short circuits between adjacent conductive structures or between adjacent contact structures. The present invention provides a semiconductor structure and a method for manufacturing a semiconductor structure, and improves connection performance by gradually reducing the size of the contact structure from the uppermost part of the contact structure to the surface of the substrate along a direction perpendicular to the substrate, that is, by making the size of the uppermost part of the contact structure relatively large, thereby making the contact area between the contact structure and the conductive structure formed later relatively large; and prevents the occurrence of a short circuit by making the distance between adjacent contact structures and adjacent conductive structures relatively far. Each embodiment of the present invention is described in detail below in conjunction with the attached drawings. However, as will be understood by those skilled in the art, many technical details are proposed in the embodiments of the present invention to help the reader better understand the embodiments of the present invention. However, the technical solution claimed in the embodiments of the present invention can be implemented without these technical details and various changes and modifications based on each of the embodiments below. In the following paragraphs, the present invention is described more specifically with reference to the drawings and through exemplary methods. The advantages and features of the present invention will become clearer in accordance with the description and claims below. It should be noted that all drawings are in a highly simplified form and all use imprecise proportions, and are intended to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understandable that the meanings of "above...", "upper side...", and "top side..." of the present invention should be interpreted in the broadest sense, and "above..." not only indicates that there is no intermediate feature or layer (located directly above the specified object) located "above" the specified object, but also includes the meaning that there is an intermediate feature or layer located "above" the specified object. In embodiments of the present invention, "first,"