KR-20260065753-A - SEMICONDUCTOR DEVICE AND METHOD OF FORMING GRAPHENE-COATED CORE EMBEDDED WITHIN TIM

Abstract

A semiconductor device has a substrate and an electrical component disposed on the substrate. The electrical component may be a semiconductor die, a semiconductor package, a surface mount device, an RF component, an isolated electrical device, or an IPD. A thermal interface material (TIM) is laminated on the electrical component. The TIM has a core, such as Cu, covered with graphene. A heat sink is disposed on the TIM, the electrical component, and the substrate. The TIM is printed on the electrical component. Graphene is interconnected within the TIM to form a thermal path from a first surface of the TIM to a second surface of the TIM opposite the first surface of the TIM. The TIM comprises a thermosetting material or a soldering-type matrix, and the graphene-covered core is embedded within the thermosetting material or soldering-type matrix. A metal layer may be formed between the TIM and the electrical component.

Inventors

• 신, 용무
• 이, 희수
• 박, 현석

Assignees

• 스태츠 칩팩 피티이. 엘티디.

Dates

Publication Date

20260511

Application Date

20260406

Priority Date

20220916

Claims (15)

1. As a semiconductor device, the semiconductor device is: Electrical components; A thermal interface material (TIM) deposited on the above electrical component - said TIM comprises a plurality of graphene-covered cores in continuous contact between a first surface of the TIM and a second surface of the TIM opposite the first surface of the TIM -; and A heat sink disposed on the second surface of the above TIM A semiconductor device characterized by including
2. A semiconductor device according to claim 1, characterized in that the plurality of graphene-covered cores form a thermal path between the first surface of the TIM and the second surface of the TIM.
3. A semiconductor device according to claim 1, characterized in that each of the plurality of graphene-covered cores includes a copper core.
4. A semiconductor device according to claim 1, wherein the TIM comprises a thermosetting material or a soldering-type matrix, and the plurality of graphene-covered cores are embedded within the thermosetting material or soldering-type matrix.
5. A semiconductor device according to claim 1, characterized in that the plurality of graphene-covered cores are arranged in a honeycomb lattice-shaped mesh network on the core material.
6. As a semiconductor device, the semiconductor device is: Electrical components; and Thermal interface material (TIM) deposited on the above electrical component Includes, The above TIM has a plurality of graphene-covered cores that connect the first surface of the TIM to the second surface of the TIM opposite the first surface of the TIM. A semiconductor device characterized by
7. A semiconductor device according to claim 6, characterized in that the plurality of graphene-covered cores form a thermal path between the first surface of the TIM and the second surface of the TIM.
8. A semiconductor device according to claim 6, characterized in that the plurality of graphene-covered cores include a copper core.
9. A semiconductor device according to claim 6, characterized in that the plurality of graphene-covered cores are arranged in a honeycomb lattice-shaped mesh network on a core material.
10. In paragraph 6, Substrate - electrical components are placed on the substrate -; and Heat sink placed on the second surface of the TIM A semiconductor device characterized by additionally comprising
11. A method for manufacturing a semiconductor device, wherein the method is: Step of providing electrical components; and Step of depositing a thermal interface material (TIM) on an electrical component Includes, Herein, the TIM comprises a plurality of graphene-covered cores that connect a first surface of the TIM to a second surface of the TIM opposite to the first surface of the TIM. A method characterized by
12. A method according to claim 11, further comprising the step of forming a thermal path through a plurality of graphene-covered cores between a first surface of the TIM and a second surface opposite the first surface of the TIM.
13. A method according to claim 11, characterized in that the plurality of graphene-covered cores include a copper core.
14. A method according to claim 11, further comprising the step of arranging the plurality of graphene-covered cores in a honeycomb grid-shaped mesh network on a core material.
15. In claim 11, the step of placing an electrical component on a substrate; and A method characterized by additionally including the step of placing a heat sink on the second surface of the TIM.

Description

Semiconductor device and method of forming a graphene-coated core embedded within a TIM The present invention generally relates to a semiconductor device, and in particular to a semiconductor device and method for heat dissipation using a graphene-coated core embedded in a thermal interface material (TIM). Background of the Invention Semiconductor devices are commonly found in modern electronic products. They perform various functions, including signal processing, high-speed computing, transmission and reception of electromagnetic signals, control of electronic devices, and the generation of visual images for optoelectronics and television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. Additionally, they are used in military applications, aviation, automobiles, industrial controllers, and office equipment. FIGS. 1a to 1c are drawings illustrating a semiconductor wafer having a plurality of semiconductor dies separated by top streets. FIGS. 2a to 2g are diagrams illustrating a process for forming a graphene Cu core within a TIM for a SiP. FIGS. 3a to 3e are drawings illustrating a process for forming a graphene Cu core. Figures 4a and 4b are diagrams illustrating additional details regarding the process of forming a graphene Cu core within a TIM. FIG. 5 is a drawing illustrating a PCB having various types of packages placed on the surface of a printed circuit board (PCB). The present invention is described below through one or more specific embodiments with reference to the drawings, where the same numbers denote identical or similar elements. Although the present invention is described based on the best method for achieving the purpose of the invention, those skilled in the art will recognize that alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention are intended to be included, as defined by the appended claims, detailed description, and drawings. Features depicted in the drawings may not necessarily be drawn to scale. Functionally similar elements are given the same reference numerals in the drawings. The term "semiconductor die" as used herein includes both singular and plural forms and can refer to both a single semiconductor device and multiple semiconductor devices. Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, function to control the flow of electric current. Passive electrical components, such as capacitors, inductors, and resistors, perform the function of an electrical circuit by creating a relationship between voltage and current. Back-end manufacturing refers to cutting or singularizing a finished wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singularize the semiconductor dies, the wafer is scored and cut along a non-functional area of the wafer called the top street or scribe. The wafer is singularized using a laser cutting tool or a saw blade. After singularization, the individual semiconductor dies are placed on a package substrate containing pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor dies are connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, stud bumps, conductive paste, or wire bonds. Encapsulation materials or other molding materials are laminated onto the package to provide physical support and electrical insulation. The finished package is inserted into an electrical system, enabling the functions of the semiconductor device to be utilized by other system components. FIG. 1a illustrates a semiconductor wafer (100) having a base substrate material (102) such as silicon, germanium, aluminum phosphate, aluminum arsenide, gallium arsenide, gallium nitride, phosphorus arsenide, silicon carbide, or other bulk materials for structural support. On the wafer (100), a plurality of semiconductor dies or components (104) are formed, separated by an inactive die-to-die wafer region or top street (106). The top street (106) provides a cutting region for individualizing the semiconductor wafer (100) into individual semiconductor dies (104). In one embodiment, the width or diameter of the semiconductor wafer (100) is 100 to 450 millimeters (mm). Alternatively, the wafer (100) may be a mold surface, an organic or inorganic substrate, or a target substrate suitable for graphene transfer. FIG. 1b is a cross-sec