KR-20260065774-A - CXL-based optical transmission mapping method

Abstract

The present invention relates to a method for optical data transmission between devices using the CXL protocol, comprising: (a) receiving electrical CXL fleet data from a host device; (b) parsing the OpCode field of the fleet header to determine CXL.cache coherent transaction and CXL.io general data; (c) separating and allocating coherent data to a low-latency optical path based on O-band single-wavelength direct intensity modulation and general data to a high-bandwidth optical path based on C-band DWDM; and (d) modulating and transmitting an optical signal through the allocated path. It includes embodiments of dynamic reallocation, BER·RTT feedback loop, prediction-based preemptive modulator activation, three-stage multipath, and MAC inline embedding, and simultaneously realizes ultra-low latency guarantee for coherent traffic and ultra-high bandwidth provision for general traffic.

Inventors

• 안범주

Assignees

• 안범주

Dates

Publication Date

20260511

Application Date

20260422

Claims (1)

1. In a method for optical data transmission between devices using the CXL protocol, (a) receiving electrical CXL fleet data from a host device; (b) a step of analyzing the header of the fleet data to determine whether transmission priority and consistency maintenance are necessary; (c) a step of separating and allocating data requiring consistency maintenance to a low-latency optical path and general data to a high-bandwidth optical path according to the above determination result; and (d) A CXL-based optical transmission mapping method comprising the step of modulating and transmitting data through the assigned optical path.

Description

CXL-based optical transmission mapping method The present invention relates to a method for transmitting data between devices using the Compute Express Link (CXL) protocol, and more specifically, to a CXL-based optical transmission mapping method that analyzes a CXL Flit header in real time to determine data requiring coherency maintenance and general data, and selectively maps each data to a low-latency optical path and a high-bandwidth optical path having physically different characteristics to modulate and transmit them as optical signals. In data center and high-performance computing environments, ultra-high-speed, low-latency data exchange between heterogeneous devices—such as host processors, accelerators, memory expanders, and smart NICs—is essential. To meet these requirements, the CXL Consortium established the CXL standard, which is based on the PCIe physical layer but dynamically multiplexes three protocol layers: CXL.io, CXL.cache, and CXL.mem. In the CXL standard, the basic unit of data transmission is the Flit (Flow Control Unit); each Flit consists of a Protocol-ID identifying the protocol type, the actual data payload, and a CRC code for error detection. The CXL.cache protocol handles snoop, request, and response transactions to maintain cache consistency between the host and the device, and due to its nature, requires extremely short round-trip latency at the level of tens of nanoseconds. On the other hand, for general data traffic transmitted via the CXL.io protocol, bandwidth—the total amount of data that can be transmitted per unit of time—is the key performance metric, rather than low latency. In conventional CXL implementations, data was transmitted and received via electrical signals of the PCIe 5.0 physical layer, specifically through high-speed serial links based on copper wire. However, copper-based interconnects have structural problems where bandwidth rapidly degrades and power consumption per bit increases as the link distance increases, due to physical limitations in signal propagation speed, conductor loss with increasing frequency, and the skin effect. In particular, it is physically very difficult to achieve the several-terabit interconnect bandwidth required by next-generation data centers using only copper wire. Optical interconnects are attracting attention as an alternative to overcome these limitations and are being actively developed in forms such as Co-Packaged Optics (CPO) and optical I/O chiplets. However, most existing research on optical interconnects has focused on maximizing bandwidth—that is, improving the total amount of data that can be transmitted per unit of time—and methodologies for differentially handling the heterogeneous Quality of Service (QoS) requirements for different traffic types demanded by the CXL protocol at the optical physical layer have not been sufficiently studied. In other words, if CXL.cache traffic for consistency maintenance and CXL.io, which is general-purpose I/O traffic, are processed through a single optical path, conflicting QoS requirements between the two traffic types may lead to increased latency for consistency traffic or wasted bandwidth for general traffic. If CXL.cache transactions are mixed with general data in the buffer of a high-bandwidth path, buffering latency and queuing latency are added, which may result in the failure to meet the latency requirements necessary for maintaining cache consistency. This can lead to violations of memory consistency across the entire system or performance degradation, and remains a fundamental challenge for the practical application of CXL-based optical interconnects. FIG. 1 is an overall system configuration diagram including a CXL-based optical transmission mapping device according to one embodiment of the present invention. Figure 2 is a detailed structural diagram showing the internal structure and header field bit arrangement of the CXL fleet. Figure 3 is a flowchart showing the overall flow of the fleet header analysis and path classification process. Figure 4 is a path configuration diagram showing the physical implementation structure of a low-latency optical path and a high-bandwidth optical path. Figure 5 is a spectral graph showing the optical wavelength arrangements assigned to the low-latency path and the high-bandwidth path. Figure 6 is a flowchart showing the flow of the path share-based dynamic reallocation process. Figure 7 is a timing diagram showing fleet processing timing during dynamic reallocation. Figure 8 is a block diagram showing the configuration of a feedback loop based on BER and RTT measurements. Figure 9 is a sequence diagram showing a path switching sequence performed only at the optical physical layer without CXL link retraining, layer by layer. Figure 10 is a block and flow diagram of the prediction-based preemptive modulator activation process. Figure 11 is a state transition diagram of FSM-based OpCode prediction. Figure 12 is a block diagram showin