KR-20260065831-A - Semi-supervised, self-supervised, and reinforcement learning machine learning models for mask prediction

Abstract

A method for training a machine learning (ML) model for generating mask patterns is disclosed, comprising: obtaining an ML model—in which the ML model is configured to generate an output mask pattern based on an input pattern—; and applying the ML model to a training input pattern to generate a predicted mask pattern, applying a forward model to the predicted mask pattern to generate a predicted wafer pattern—in which the forward model is configured to predict an output wafer pattern based on the input mask pattern—and training the ML model by determining the difference between a target wafer pattern and a predicted wafer pattern, and adjusting the ML model based on the difference between the target wafer pattern and the predicted wafer pattern. Additionally, a method for training a generative model to generate mask patterns is provided. Some embodiments provide model improvement through reinforcement learning that may be used with any other model provided.

Inventors

• 오노세, 알렉산드루
• 왕, 젠-시앙
• 스펜스, 크리스토퍼, 앨런
• 타오, 준
• 카오, 유
• 피사렌코, 맥심
• 반 크라이이, 마르쿠스, 제라르두스, 마르티누스, 마리아
• 부네, 로버트, 엘리엇
• 하무다, 아이만
• 루이스, 한스-크리스티안
• 루오, 야
• 루, 옌-웬
• 첸, 빈-데르
• 호웰, 라파엘 씨.

Assignees

• 에이에스엠엘 네델란즈 비.브이.

Dates

Publication Date

20260511

Application Date

20240807

Priority Date

20230905

Claims (15)

1. As a computer-implemented method for training a machine learning (ML) model for mask pattern generation, Step of obtaining the above ML model - the above ML model is configured to generate an output mask pattern based on an input pattern - ; and Step of training the above ML model Includes, and the above training is: Generating a predicted mask pattern by applying the above ML model to a training input pattern; Generating a predicted wafer pattern by applying a forward model to the above-mentioned predicted mask pattern - the above-mentioned forward model is configured to predict an output pattern based on an input mask pattern - ; Determining the difference between the above training input pattern and the above predicted wafer pattern; and Performed by adjusting the ML model based on the difference between the training input pattern and the predicted wafer pattern, Computer-implemented method.
2. In Article 1, Training the ML model by applying the ML model to the above training input pattern includes training the ML model by unsupervised training. Computer-implemented method.
3. In Article 2, Further comprising training the ML model by semi-supervised learning, unsupervised learning, and/or self-supervised learning on one or more additional training input patterns, Each of the above one or more additional training input patterns includes a subpattern of the design layout, Computer-implemented method.
4. In Article 2, Training the above ML model is: Further comprising training the ML model based on a set of supervised training data, wherein the supervised training data set comprises a set of supervised training patterns and corresponding training mask patterns. Computer-implemented method.
5. In Article 4, The above ML model and the above forward model generate outputs at different time intervals, and (i) training the ML model based on the supervised training data set, and (ii) training the ML model by the above unsupervised learning occur asynchronously. Computer-implemented method.
6. In Article 5, Adjusting the ML model based on the difference between the training input pattern and the predicted wafer pattern substantially occurs after the forward model has generated the predicted wafer pattern, Computer-implemented method.
7. In Article 4, The above supervised training patterns are ground truth wafer patterns for the corresponding training mask patterns, and the above supervised training patterns are selected by a pattern selection algorithm, Computer-implemented method.
8. In Article 4, The training input pattern of the above unsupervised learning is not a member of the set of supervised training patterns of the above supervised training dataset, Computer-implemented method.
9. In Article 4, (i) training the ML model based on the supervised training dataset, and (ii) training the ML model by unsupervised learning comprises (i) the difference between the training mask patterns of the supervised training dataset and the mask patterns predicted by the ML model based on the supervised training patterns of the supervised training dataset, and (ii) adjusting the ML model based on the difference between one or more training input patterns and one or more predicted wafer patterns. Computer-implemented method.
10. In Article 9, (i) the difference between the training mask patterns of the supervised training dataset and the mask patterns predicted by the ML model based on the supervised training patterns of the supervised training dataset, and (ii) the difference between one or more training input patterns and one or more predicted wafer patterns, wherein the first part of the cost function and the second part of the cost function are related by hyperparameters, and said hyperparameters evolve over the training, Computer-implemented method.
11. In Article 1, The step of training the ML model comprises adjusting at least one of the parameters, shape, or combination thereof of the ML model until a termination criterion is reached, wherein the termination criterion is at least one of a gradient value, a loss function value, a cost function value, a number of iterations, an execution time, receiving additional outputs of the forward model, or a combination thereof. Computer-implemented method.
12. In Article 1, The method further includes the step of determining a loss function based on the difference between the training input pattern and the predicted wafer pattern, and adjusting the ML model includes adjusting the ML model based on the loss function. Computer-implemented method.
13. In Article 1, The above output mask pattern comprises at least one of a mask layout, an aerial image, a mask image, a continuous transmission mask (CTM) pattern, and a combination thereof. Computer-implemented method.
14. In Article 1, The above ML model is based on a neural network (NN), and The above forward model is a non-machine learning (non-ML) model, Computer-implemented method.
15. In Article 1, The above forward model is at least one of an optical model, an etching model, a resist model, a lithography model, a physical model, and a combination thereof, and The above forward model is not substantially changed by the above training, Computer-implemented method.

Description

Semi-supervised, self-supervised, and reinforcement learning machine learning models for mask prediction This application claims priority to US application 63/536,696 filed September 5, 2023 and US application 63/625,134 filed January 25, 2024, the full text of which is incorporated herein by reference. The present disclosure generally relates to lithography process modeling and a method for generating mask predictions based on a process model using a machine learning (ML) model. A lithography projection device may be used, for example, in the manufacture of an integrated circuit (IC). A patterning device (e.g., a mask) may include or provide a pattern ("design layout") corresponding to an individual layer of the IC, and this pattern may be transferred onto a target area (e.g., comprising one or more dies) on a substrate (e.g., a silicon wafer) coated with a layer of radiation-sensitive material ("resist") by methods such as irradiating the target area through the pattern on the patterning device. Generally, a single substrate comprises a plurality of adjacent target areas on which the pattern is transferred sequentially, one target area at a time, by the lithography projection device. Before transferring a pattern from a patterning device to a substrate, the substrate may undergo various procedures such as priming, resist coating, and soft baking. After exposure, the substrate may undergo other procedures ("post-exposure procedures") such as post-exposure bake (PEB), development, hard baking, and measurement/inspection of the transferred pattern. This series of procedures serves as the basis for forming individual layers of a device, such as an IC. Subsequently, the substrate may undergo various processes such as etching, ion implantation (doping), metallization, oxidation, and chemical-mechanical polishing, all of which are intended to finish the individual layers of the device. If multiple layers are required in the device, the entire process or a variation thereof is repeated for each layer. Finally, the device will be present on each target area of the substrate. Then, these devices are separated from each other by techniques such as dicing or sawing, allowing the individual devices to be mounted on a carrier, such as one connected to pins. Accordingly, manufacturing devices such as semiconductor devices typically involves processing a substrate (e.g., a semiconductor wafer) using multiple fabrication processes to form various features and multiple layers of the devices. These layers and features are typically fabricated and processed using, for example, deposition, lithography, etching, chemical-mechanical polishing, and ion implantation. After the devices are fabricated on multiple dies of the substrate, they can be separated into individual devices. This device manufacturing process can be considered a patterning process. The patterning process involves a patterning step, such as optical and/or nanoimprint lithography, using a patterning device in a lithography device to transfer a pattern on the patterning device onto the substrate, and typically but optionally involves one or more related pattern processing steps, such as resist development by a developing device, baking of the substrate using a baking tool, and etching of the pattern using an etching device. As is noted, lithography is a central step in the manufacturing of devices such as ICs, where patterns formed on substrates define the functional elements of devices such as microprocessors and memory chips. Additionally, similar lithography techniques are used in the formation of flat panel displays, MEMS (micro-electromechanical systems), and other devices. As semiconductor manufacturing processes continue to advance, the dimensions of functional elements have continued to decrease, while the number of functional elements, such as transistors per device, has steadily increased over the decades, following a trend generally known as "Moore's Law." At the current level of technology, layers of devices are manufactured using lithography projection devices that project a design layout onto a substrate using illumination from a deep ultraviolet light source, creating individual functional elements with dimensions much lower than 100 nm—that is, dimensions smaller than half the wavelength of radiation from an illumination source (e.g., a 193 nm light source). This process, in which features with dimensions smaller than the typical resolution limit of a lithography projection device are printed, is generally known as low- k1 lithography according to the resolution formula CD = k1 × λ/NA, where λ is the wavelength of the radiation adopted (currently, in most cases, 248 nm or 193 nm), NA is the numerical aperture of the projection optics within the lithography projection device, CD is the "critical dimension"—typically, the minimum feature size to be printed—and k1 is an empirical resolution factor. Generally, the smaller k1 is, the more difficult it