KR-20260065890-A - Device and method for half-page mode of a memory device

Abstract

An apparatus, system, and method for a half-page mode are disclosed. A memory device may operate in a full-page mode, where all memory cells along a word line are used for data, or in a half-page mode, where fewer than all memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by parts of different word lines. In some half-page modes, data may be stored in a selected part of the memory cell, and additional information, such as metadata or module parity, may be stored in an unselected part of the memory cell. Additional information may be provided along additional data terminals so as not to increase the data burst length.

Inventors

• 아야푸레디, 수지트

Assignees

• 마이크론 테크놀로지, 인크.

Dates

Publication Date

20260511

Application Date

20240723

Priority Date

20230905

Claims (20)

1. As a device, A word line coupled to a first plurality of memory cells and a second plurality of memory cells; A row decoder configured to selectively activate the first plurality or the second plurality of memory cells based on a row address in a first mode, and configured to activate the first plurality and the second plurality of memory cells based on the row address in a second mode. A device including
2. A device according to claim 1, further comprising a column decoder configured to receive a column address, wherein the column address does not change in length between the first mode and the second mode.
3. In claim 1, the row address is a device having a first length in the first mode and a second length in the second mode.
4. A device according to paragraph 3, wherein the first length is longer than the second length, and in the first mode, the row address includes a row driver select bit.
5. A device according to claim 1, wherein the row decoder is configured to activate a first number of memory cells in the first mode and activate a second number of memory cells in the second mode.
6. A device according to claim 1, wherein the first mode is a half-page mode and the second mode is a full-page mode.
7. A device according to claim 1, wherein the word line comprises a first portion coupled to the first plurality of memory cells and a second portion coupled to the second plurality of memory cells.
8. As a device, A word line comprising a first portion and a second portion, wherein the first portion is coupled to a first plurality of memory cells and the second portion is coupled to a second plurality of memory cells; A first row driver coupled to the first part above; A second row driver coupled to the second part above; and A row decoder configured to selectively enable the first row driver or the second row driver based on the row driver selection bit of the row address A device including
9. A device according to claim 8, wherein the row decoder is configured to selectively activate the first row driver or the second row driver based on the row driver select bit of the row address in a first mode, and configured to activate the first row driver and the second row driver based on the row address in a second mode.
10. In claim 9, the row address is a device that does not include the row driver select bit in the second mode.
11. A device according to claim 9, wherein the first mode is a half-page mode and the row address includes a first number of bits, and the second mode is a full-page mode and the row address includes a second number of bits different from the first number.
12. A device according to claim 8, further comprising a column decoder configured to provide a column selection signal to the first part and the second part based on a column address.
13. A device according to claim 8, wherein the first portion is not coupled to the second plurality of memory cells, and the second portion is not coupled to the first plurality of memory cells.
14. In claim 8, the device wherein the first plurality of memory cells has the same number of memory cells as the second plurality of memory cells.
15. As a method, A step of receiving multiple data bits and row addresses; A step of selecting one of the first or second parts of a word line based on the row driver selection bit of the above row address; Step of activating one of the selected first or second parts of the above word line; and Step of writing the plurality of data bits to a memory cell following the activated selected one of the first or second part of the word line. A method including
16. In paragraph 15, A method further comprising the step of activating the first part using a first row driver or activating the second part using a second row driver.
17. In paragraph 15, Receiving the row address including the row driver select bit in half-page mode; and Receiving the row address that does not include the row driver selection bit in full-page mode A method that additionally includes
18. In paragraph 15, A step of generating a plurality of parity bits based on the plurality of data bits using an error correction circuit; and Step of writing the plurality of parity bits to the memory cell following the activated selected one of the first or second part of the word line. A method that additionally includes
19. In paragraph 15, A method further comprising the step of providing a column selection signal to a first plurality of column planes following the first portion of the word line and a second plurality of column planes following the second portion of the word line, based on a column address.
20. A method according to claim 15, further comprising the step of receiving the plurality of data bits following the first data terminal and the second data terminal as part of a 2p2 mode.

Description

Device and method for half-page mode of a memory device Cross-reference regarding related applications This application claims the benefit of 35 U.S.C. §119 of the original filing date of U.S. provisional application serial number 63/580,506 filed September 5, 2023, the entire contents of which are incorporated herein by reference for any purpose. The present disclosure generally relates to semiconductor devices, and more specifically to semiconductor memory devices. In particular, the present disclosure relates to volatile memory such as dynamic random access memory (DRAM). Information may be stored in individual memory cells of the memory as a physical signal (e.g., charge in a capacitive element). During an access operation, an access command may be received along with address information specifying which memory cell should be accessed. Memory devices may be packaged together as a module. There is growing interest in increasing the efficiency of memory devices and memory modules to reduce unnecessary power consumption during operation and to enable the inclusion of additional information in the module. Certain memory modes may involve accessing fewer bits than the maximum number of bits that can be accessed at once. To improve efficiency, there may be a need for various improvements regarding how these bits are accessed and/or how bits that are not accessed are used. FIG. 1 is a block diagram of a memory system according to some embodiments of the present disclosure. FIG. 2 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. FIG. 3 is a block diagram of a memory device according to some embodiments of the present disclosure. FIG. 4 is a block diagram of a part of a memory device according to some embodiments of the present disclosure. FIG. 5 is a block diagram of information storage in a memory array operating in half-page mode without any additional information, according to some embodiments of the present disclosure. FIG. 6 is a flowchart of a method for recording data in half-page mode according to some embodiments of the present disclosure. FIG. 7 is a flowchart of a method for reading data and additional information from a memory device according to some embodiments of the present disclosure. FIG. 8 is a block diagram of information storage in a memory array operating in a half-page mode having module parity, such as an 8x2p3 high reliability mode according to some embodiments of the present disclosure. FIG. 9 is a block diagram of a method in which data and module parity are transmitted along a DQ terminal according to some embodiment of the present disclosure. FIG. 10 is a flowchart of a method for recording data and module parity in a memory device according to some embodiments of the present disclosure. FIG. 11 is a block diagram of information storage in a memory array operating in a half-page mode having additional information, such as an 8x2p3 high-reliability mode with metadata enabled according to some embodiments of the present disclosure. FIG. 12 is a block diagram of a method in which data and module parity are transmitted along a DQ terminal according to some embodiment of the present disclosure. FIG. 13 is a flowchart of a method for providing additional information following an additional data terminal when additional information according to some embodiment of the present disclosure is activated. FIG. 14 is a block diagram of a method in which data and module parity are transmitted along a DQ terminal according to some embodiment of the present disclosure. FIG. 15 is a method for switching between module parity modes according to some embodiments of the present disclosure. The following description of specific embodiments is merely illustrative and is not intended to limit the scope, application, or use of the present disclosure. In the following detailed description of the embodiments of the system and method, reference is made to the accompanying drawings, which form part of this specification and illustrate, by example, specific embodiments in which the described system and method may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the system and method disclosed herein, and it should be understood that other embodiments may be utilized and structural and logical modifications may be made without departing from the spirit and scope of the present disclosure. Furthermore, for clarity, detailed descriptions of specific features will not be discussed where they would be obvious to those skilled in the art so as not to obscure the description of the embodiments of the present disclosure. Accordingly, the following detailed description should not be taken in a limiting sense, and the scope of the present disclosure is limited only by the appended claims. A memory array may generally include a number of memory cells arranged at the intersection of word lines (rows) and bit li