KR-20260066023-A - SEMICONDUCTOR DEVICE

Abstract

A semiconductor device according to one embodiment includes a cell region and a circuit region located overlapping with the cell region, wherein the circuit region includes a substrate, a through-contact penetrating the substrate, and an insulating film located between the substrate and the through-contact, wherein the substrate adjacent to the through-contact includes a doping region, wherein the doping region is located surrounding the through-contact in a planar manner, and the doping region is doped with a conductivity type opposite to that of the substrate.

Inventors

• 이태희
• 오창욱

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20260423

Claims (10)

1. It includes a cell region and a circuit region located overlapping with the cell region, and The above circuit area is Substrate; A through contact penetrating the above substrate; It includes an insulating film located between the substrate and the through contact, The substrate includes a doping region located adjacent to the through contact. The above doping region is located in a planar manner surrounding the above through contact, and A semiconductor device in which the doping region is doped with a conductivity type opposite to that of the substrate.
2. In Paragraph 1, A semiconductor device in which the above-mentioned doping region is a neutral region.
3. In Paragraph 1, The above doping region is a semiconductor device doped with P or As.
4. In Paragraph 1, A semiconductor device in which the insulating film located between the substrate and the through-contact is a porous insulating film.
5. In Paragraph 1, A groove formed on the substrate and surrounding the through contact in a planar manner; A via connected to the area between the above groove and the above through contact; A semiconductor device including a second wiring connected to the above via.
6. In paragraph 5, A semiconductor device in which the insulating film located between the substrate and the through-contact is a porous insulating film.
7. In Paragraph 1, A semiconductor device in which the planar shape of the doping region is ring-shaped.
8. It includes a cell region and a circuit region located overlapping with the cell region, and The above circuit area is Substrate; A through contact penetrating the substrate; and It includes an insulating film located between the substrate and the through contact, It is located on the substrate adjacent to the through contact and includes a groove that surrounds the through contact in a planar manner. A semiconductor device comprising a via connected to an area between the above-mentioned groove and the above-mentioned through-contact, and wiring connected to the above-mentioned via.
9. In paragraph 8, The above-mentioned through contact is located within the area partitioned by the groove, and The region partitioned by the above groove is a semiconductor device that receives voltage from the above via and the above wiring.
10. In paragraph 8, A semiconductor device in which the insulating film located between the substrate and the through-contact is a porous insulating film.

Description

Semiconductor Device The present disclosure relates to a semiconductor device. In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor devices are being researched. For example, as one method to increase the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. FIG. 1 briefly illustrates a cross-section of a semiconductor device according to one embodiment. Figure 2 illustrates the planar shape of the through contact and surrounding area of Figure 1. Figure 3 illustrates the cell area of Figure 1. FIG. 4 is a partial cross-sectional view illustrating an example of a channel structure included in the semiconductor device illustrated in FIG. 3. FIG. 5 illustrates the area indicated by A in FIG. 1 for another embodiment. Figure 6 illustrates the planar shape of the through contact and surrounding area of Figure 5. FIG. 7 illustrates the area indicated as A in FIG. 1 for another embodiment. FIG. 8 illustrates the same area as FIG. 5 for another embodiment. FIG. 9 illustrates the same area as FIG. 5 for another embodiment. FIG. 10 illustrates the same area as FIG. 9 for another embodiment. FIGS. 11 to 16 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment. FIGS. 17 to 22 illustrate a method for manufacturing a semiconductor device according to another embodiment. Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein. To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification. Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings. Furthermore, when it is said that a part, such as a layer, membrane, region, or plate, is "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. Also, saying that a part is "on" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "on" in the direction opposite to gravity. Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side. Then, a semiconductor device according to the present embodiment will be described below with reference to the drawings. FIG. 1 briefly illustrates a cross-section of a semiconductor device according to one embodiment. Referring to FIG. 1, the semiconductor device according to the present embodiment may include a cell region (400) in which a memory cell structure is provided, and a circuit region (300) in which a peripheral circuit structure for controlling the operation of the memory cell structure is provided. As illustrated in FIG. 1, a circuit region (300) may be positioned on a cell region (400). The semiconductor device according to the present embodiment may have a structure in which the circuit region (300) is positioned on the cell region (400). In this case, the length of the contact connecting the cell region (400) and the circuit region (300) is shortened, thereby minimizing parasitic capacitance caused by the contact. However, when the cell region (400) is positioned on the circuit region (300), the contact penetrates the first substrate (200), so capacitance may occur between the through-contact (TSV) and the first substrate (200). The present embodiment relates to a structure for minimizing capacitance between the through-contact (TSV) penetrating the first substrate (200) and the first substrate (200). Th