KR-20260066077-A - Analog-to-digital method for joint clock recovery and frame alignment

Abstract

The receiver (20) includes (i) a circuit comprising a clock and data recovery (CDR) loop and (ii) a frame aligner (84). The circuit is configured to apply CDR to a signal using the CDR loop and to buffer the signal that has undergone CDR into a memory buffer (60). The frame aligner (84) is configured to align the signal buffered in the memory buffer (60) to the frame boundary between consecutive frames of the signal by applying one or more shifts to the CDR loop, each corresponding to the symbol duration of the signal.

Inventors

• 나디리 오어
• 도르만 가이
• 하렐 알론

Assignees

• 레팀 인코포레이티드

Dates

Publication Date

20260512

Application Date

20240430

Priority Date

20230907

Claims (14)

1. As a receiver, A circuit including a clock and data recovery (CDR) loop - said circuit is configured to apply CDR to a signal using said CDR loop and buffer said signal, after passing through CDR, into a memory buffer - ; and A receiver characterized by including a frame aligner configured to align the signal buffered in the memory buffer to the frame boundary between consecutive frames of the signal by applying one or more shifts corresponding to the symbol duration of the signal to the CDR loop.
2. In paragraph 1, The above circuit includes a processing chain configured to sample the signal according to a sampling clock, resample the sampled signal according to a resampling phase, and buffer the resampled signal in the memory buffer; The above CDR loop includes (i) a first CDR loop configured to adjust the sampling clock and (ii) a second CDR loop configured to adjust the resampling phase; A receiver characterized in that the frame aligner is configured to align the signal buffered in the memory buffer to the frame boundary by applying the one or more shifts to both the first CDR loop and the second CDR loop.
3. A receiver according to paragraph 2, characterized in that the first CDR loop has a first loop bandwidth, and the second CDR loop has a second loop bandwidth greater than the first loop bandwidth.
4. A receiver according to paragraph 2, wherein the circuit includes a numerically controlled oscillator (NCO) configured to adjust the sampling phase of the first and second CDR loops, and the frame aligner is configured to apply the shift by controlling the NCO.
5. A receiver according to any one of claims 1 to 4, wherein the circuit is configured to detect the frame synchronization sequence in the signal when the signal is buffered within the memory buffer up to the frame boundary, and the frame aligner is configured to continue applying the shift until the frame synchronization sequence is detected.
6. A receiver characterized in that, in any one of claims 1 to 4, the frame aligner is configured to apply each of the shifts during different frames of the signal.
7. A receiver characterized in that, in any one of claims 1 to 4, the frame aligner is configured to insert a waiting period after every N shift, and N is a defined integer.
8. A step of applying clock and data recovery (CDR) to the signal using a CDR loop; A step of buffering the above signal, which has passed through CDR, into a memory buffer; A step of aligning the signal buffered in the memory buffer to the frame boundary between consecutive frames of the signal by applying one or more shifts corresponding to the symbol duration of the signal to the CDR loop; and A method characterized by including the step of applying additional processing to the aligned signal within the memory buffer.
9. In paragraph 8, The step of applying the above CDR loop includes (i) adjusting the sampling clock of the signal by the first CDR loop and (ii) adjusting the resampling phase of the signal by the second CDR loop; A method characterized by the step of aligning the above signals including the step of applying the one or more shifts to both the first CDR loop and the second CDR loop.
10. A method according to claim 9, characterized in that the first CDR loop has a first loop bandwidth, and the second CDR loop has a second loop bandwidth greater than the first loop bandwidth.
11. A method according to claim 9, wherein the step of aligning the signal comprises the step of applying the shift to a numerically controlled oscillator (NCO) that adjusts the sampling phase of the first and second CDR loops.
12. A method according to any one of claims 8 to 11, wherein the step of aligning the signal includes the step of continuously applying the shift until a frame synchronization sequence is detected in the signal, characterized in that the signal buffered in the memory buffer is aligned to the frame boundary.
13. A method characterized in that, in any one of claims 8 to 11, the step of aligning the signal includes the step of applying each shift during different frames of the signal.
14. A method characterized in that, in any one of claims 8 to 11, the step of aligning the signal includes the step of inserting a waiting interval after every N shift, wherein N is a defined integer.

Description

Analog-to-digital method for joint clock recovery and frame alignment (Refer to related application) This application claims priority to U.S. provisional patent application No. 63/581,007 filed on September 7, 2023, the disclosure of which is incorporated herein by reference. (Field of Invention) The present invention generally relates to a communication receiver, and in particular to a method and system for common clock recovery and frame alignment. Communication receivers often perform tasks such as Clock and Data Recovery (CDR) and Frame Alignment. CDR generally involves recovering the clock signal from the received signal to establish appropriate timing for sampling the signal. Frame Alignment generally involves identifying the timing of the signal frame and aligning the in-memory storage of the received signal to the frame boundaries for further processing. FIG. 1 is a block diagram schematically illustrating a receiver using a joint CDR and frame alignment according to an embodiment of the present invention. FIG. 2 is a block diagram schematically illustrating a buffer before and after frame alignment in the receiver of FIG. 1 according to an embodiment of the present invention. FIG. 3 is a state diagram schematically illustrating a frame alignment process according to an embodiment of the present invention. FIGS. 4 and 5 are graphs of simulation results showing the operation of the CDR loop in the receiver of FIG. 1 during joint CDR and frame alignment according to an embodiment of the present invention. (outline) Overview The embodiments of the invention described herein provide a method and apparatus for common clock and data recovery (CDR) and frame alignment within a communication receiver. In the disclosed embodiment, a receiver receives a signal containing a sequence of signal frames. The receiver processes the signal, including recovering the signal clock using a CDR loop, during other tasks. The receiver buffers the signal that has passed through the CDR in a memory buffer for further processing (e.g., carrier phase recovery and/or bit decoding). Each frame of the signal contains a frame synchronization sequence, for example, a Start-Of-Frame (SOF) sequence used by a receiver to detect frame boundaries. To simplify subsequent processing of the signal, it is required that the signal be aligned to the frame boundaries within the buffer. That is, the signal needs to be stored in the buffer such that the frame synchronization sequence is located at a fixed, predefined position (“target position”) within the buffer. To meet these requirements, the receiver additionally includes a frame aligner that aligns the signals within the buffer by controlling the CDR loop. Generally, although not mandatory, the frame aligner is implemented in software. The frame aligner performs an iterative process of shifting the timing of the signals from one frame to another by one symbol duration (one unit interval (UI)). As a result of the timing shift, the position of the frame synchronization sequence within the buffer moves one symbol-position from frame to frame. The process continues until the frame synchronization sequence reaches the target position within the buffer. In a given iteration of the process, the frame aligner shifts the timing of the signal by 1·UI by controlling the CDR loop to apply an additional phase shift corresponding to one symbol duration. In an exemplary implementation described in detail herein, the CDR loop is a dual loop comprising (i) a slower CDR loop that adapts the sampling clock used to sample the signal and (ii) a faster CDR loop that adapts the resampling phase used to resample the signal. A numerically controlled oscillator (NCO) generates a digital phase correction word that specifies the resampling phase, which in turn generates the sampling clock after further processing. Thus, the NCO is considered to belong to both CDR loops. The frame aligner controls the NCO to apply an additional phase bias corresponding to a 1·UI timing shift in each iteration. When using the disclosed technology, the same CDR loop is used for both clock recovery (at sub-UI resolution and with 1·UI ambiguity) and frame alignment (at integer multiples of 1·UI). As described and demonstrated herein, the two operations are performed simultaneously with little to no mutual influence on each other. This solution minimizes the additional hardware required for frame alignment. Consequently, power consumption is significantly reduced, particularly within highly parallelized receiver configurations. The disclosed technique can also be shown as a circuit that converges to sample a received signal at an appropriate phase having two different resolutions: (i) a sub-UI resolution with 1·UI ambiguity based on timing error estimation, and (ii) a resolution at an integer multiple of 1·UI based on frame synchronization detection. The disclosed technology is demonstrated below using a receiver configuration that performs