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KR-20260066080-A - Semiconductor device and method of manufacturing a semiconductor device

KR20260066080AKR 20260066080 AKR20260066080 AKR 20260066080AKR-20260066080-A

Abstract

A semiconductor device comprising a plurality of lower layer conductive patterns formed on the upper surface of a substrate, a first insulating film formed on the upper surface of the substrate that fills the spaces between the plurality of lower layer conductive patterns, a plurality of upper layer conductive patterns formed on the first insulating film that are bonded to the plurality of lower layer conductive patterns, and a second insulating film formed on the first insulating film that fills the spaces between the plurality of upper layer conductive patterns, wherein a concave portion is provided from the upper surface of the first insulating film, with the upper surface of the lower layer conductive pattern as the bottom surface, and in the portion where the lower layer conductive pattern and the upper layer conductive pattern are misaligned, a bonding portion is provided within the concave portion such that the upper layer conductive pattern is positioned lower than the upper surface of the first insulating film, and the upper layer conductive pattern is bonded to the lower layer conductive pattern so as to cover the entire surface of the upper surface of the lower layer conductive pattern.

Inventors

  • 우사미 다츠야

Assignees

  • 라피더스 가부시키가이샤

Dates

Publication Date
20260512
Application Date
20240626
Priority Date
20230919

Claims (14)

  1. A plurality of lower layer conductive patterns formed on the upper side of the substrate, and A first insulating film formed above the substrate that fills the plurality of lower layer conductive patterns, and A plurality of upper layer conductive patterns formed on the first insulating film that is bonded to the plurality of lower layer conductive patterns, and A second insulating film formed on the first insulating film that fills the space between the plurality of upper layer conductive patterns, and A concave portion is provided from the upper surface of the first insulating film, with the upper surface of the lower conductive pattern as the bottom surface, and In the portion where the lower conductive pattern and the upper conductive pattern are misaligned, there is a junction in which the upper conductive pattern is located lower than the upper surface of the first insulating film within the concave portion. A semiconductor device in which the upper conductive pattern is bonded to the lower conductive pattern so as to cover the entire surface of the upper portion of the lower conductive pattern.
  2. In paragraph 1, A semiconductor device in which the step difference between the upper surface of the first insulating film and the upper surface of the junction in the upper layer conductive pattern is 30% or more of the minimum gap between the lower layer conductive patterns and between the upper layer conductive patterns.
  3. In paragraph 2, A semiconductor device in which the depth of the above-mentioned concave portion is at least 1/3 of the above-mentioned minimum interval.
  4. In paragraph 1, A semiconductor device having a barrier insulating layer provided on the upper surface of the first insulating film and on the side wall of the concave portion.
  5. In paragraph 1, A first lower barrier insulating layer is provided on the lower layer of the first insulating film and on the side wall of the first insulating film, and A semiconductor device having a second lower barrier insulating layer provided on the lower layer of the second insulating film and on the side wall of the second insulating film.
  6. In paragraph 1, The first insulating film has a cavity between the lower conductive patterns, and The above second insulating film is a semiconductor device having a cavity between the upper layer conductive patterns.
  7. In paragraph 1, A semiconductor device having a barrier metal layer provided at the bottom of the lower conductive pattern and at the bottom of the upper conductive pattern.
  8. In Paragraph 7, The above lower conductive pattern and the above upper conductive pattern are composed of wiring and vias above the wiring, and A semiconductor device having an intermediate barrier metal layer provided between the above wiring and via.
  9. In paragraph 1, The upper layer conductive pattern is composed of an anchor portion provided within the concave portion and a main body layer provided on the upper surface of the anchor portion and the upper surface of the first insulating film, and A semiconductor device in which the anchor portion and the main body layer are made of different conductive materials.
  10. In paragraph 1, The upper layer conductive pattern is composed of a wiring lower layer provided within the concave portion and on the upper surface of the first insulating film, and a main body layer provided on the upper surface of the wiring lower layer. A semiconductor device in which the above-mentioned wiring lower layer and the above-mentioned main body layer are made of different conductive materials.
  11. A process of forming a plurality of lower layer conductive patterns on the upper side of a substrate, and A process of forming a first insulating film on the upper side of the substrate that fills the space between the plurality of lower layer conductive patterns, and A process of forming a concave portion having the upper surface of the lower conductive pattern as the bottom surface from the upper surface of the first insulating film by removing a recess from the upper portion of the lower conductive pattern exposed on the upper surface of the first insulating film, and A process of forming a plurality of upper layer conductive patterns bonded to the plurality of lower layer conductive patterns by patterning a conductive film formed on the lower layer conductive pattern and the first insulating film, and A process for forming a second insulating film on the first insulating film that fills the space between the plurality of upper layer conductive patterns, and In the process of forming the upper layer conductive pattern above, After patterning the conductive film by anisotropic etching until the first insulating film is exposed, A method for manufacturing a semiconductor device, wherein in a portion where the lower conductive pattern and the upper conductive pattern are misaligned, the conductive film is further anisotropically etched so as to leave the conductive film on the entire surface of the upper portion of the lower conductive pattern within the concave portion.
  12. In Paragraph 11, The above lower layer conduction pattern is composed of a sacrificial layer at the top, and A method for manufacturing a semiconductor device, wherein when removing the upper portion of the lower conductive pattern, the sacrificial layer is selectively removed to form the concave portion to a depth corresponding to the film thickness of the sacrificial layer.
  13. In Paragraph 11, In the process of forming the upper layer conductive pattern above, An anchor portion of the conductive film is formed within the concave portion by selective growth of the lower layer conductive pattern, and then, a main body layer of the conductive film is formed on the upper portion of the anchor portion and on the first insulating film, the main body layer of the conductive film being made of a conductive material different from the anchor portion. A method for manufacturing a semiconductor device, wherein the main body layer is etched by etching with a high selectivity ratio with respect to the anchor portion, and then the upper layer conductive pattern is formed by etching the anchor portion.
  14. In Paragraph 11, In the process of forming the upper layer conductive pattern above, A wiring lower layer of the conductive film is formed within the above-mentioned concave portion and on the upper surface of the first insulating film, and then, a main body layer of the conductive film is formed using a conductive material different from the wiring lower layer. A method for manufacturing a semiconductor device, wherein the main body layer is etched by etching with a high selectivity ratio with respect to the lower wiring layer, and then the upper layer conductive pattern is formed by etching the lower wiring layer.

Description

Semiconductor device and method of manufacturing a semiconductor device The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. As a technology relating to a semiconductor device and a method for manufacturing a semiconductor device, the following manufacturing method is described in Patent Document 1. First, a plurality of conductive vias embedded in a first dielectric layer are selectively etched to form a recess on the conductive via in the first dielectric layer. Next, a second dielectric layer is formed on the upper surface of the first dielectric layer and the conductive via through an etching stop layer. Next, a trench connected to each conductive via is formed in the second dielectric layer and the etching stop layer, and a conductive layer is filled into the trench and the recess on the conductive via. By doing so, compared to a configuration in which the entire upper surface of the conductive via is placed on the same plane as the surface of the first dielectric layer, the distance between any conductive via and the conductive layer formed in the trench on the conductive via adjacent thereto is increased (see Patent Document 1, FIG. 7 above). FIG. 1 is a cross-sectional view of the main part of a semiconductor device of a first embodiment. Figure 2 is an enlarged view of part A of Figure 1. FIG. 3 is a process diagram (the 1) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 4 is a process diagram (the 2) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 5 is a process diagram (the 3) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 6 is a process diagram (the 4) showing a method for manufacturing a semiconductor device of the first embodiment. FIG. 7 is a process diagram (the 5) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 8 is a process diagram (the 6) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 9 is a process diagram (the 7) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 10 is a process diagram (the 8) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 11 is a process diagram (the 9) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 12 is a process diagram (the 10) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 13 is a process diagram (the 11) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 14 is a process diagram (the 12) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 15 is a process diagram (the 13) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 16 is a process diagram (the 14) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 17 is a process diagram (the 15) showing a method for manufacturing a semiconductor device of a first embodiment. FIG. 18 is a cross-sectional view of another part of a semiconductor device of the first embodiment. FIG. 19 is a cross-sectional view of the main part of a semiconductor device of a second embodiment. FIG. 20 is a cross-sectional view of another part of a semiconductor device of a second embodiment. FIG. 21 is a cross-sectional view of the main part of a semiconductor device of a third embodiment. FIG. 22 is a cross-sectional view of another part of a semiconductor device of the third embodiment. FIG. 23 is a cross-sectional view of the main part of a semiconductor device of the fourth embodiment. FIG. 24 is a cross-sectional view of another part of a semiconductor device of the fourth embodiment. FIG. 25 is a process diagram (the 1) showing a method for manufacturing a semiconductor device of a fourth embodiment. FIG. 26 is a process diagram (the 2) showing a method for manufacturing a semiconductor device of a fourth embodiment. FIG. 27 is a cross-sectional view of the main part of a semiconductor device of the fifth embodiment. FIG. 28 is a cross-sectional view of another part of a semiconductor device of the fifth embodiment. FIG. 29 is a cross-sectional view of the main part of a semiconductor device of the 6th embodiment. FIG. 30 is a cross-sectional view of another part of a semiconductor device of the sixth embodiment. FIG. 31 is a process diagram (the 1) showing a characteristic part of a method for manufacturing a semiconductor device of the 6th embodiment. FIG. 32 is a process diagram (the 2) showing a characteristic part of a method for manufacturing a semiconductor device of the 6th embodiment. FIG. 33 is a cross-sectional view of the main part of a semiconductor device of the seventh embodiment. FIG. 34 is a process diagram (the 1) showing a characteristic part of a method for manufacturing a semiconductor