KR-20260066099-A - BUMPLESS SUPERCONDUCTOR DEVICE

Abstract

An integrated circuit (50) is provided comprising a plurality of conductive contact pads (60) on the surface of a first substrate (52) and a dielectric layer (54) placed on the first substrate and the conductive contact pads, wherein the conductive contact pads are coupled to each qubit (62). A second substrate (56) is placed on the dielectric layer, and a plurality of superconducting contacts (58) extend through the second substrate and the dielectric layer, such that each superconducting contact is aligned with and contacts each conductive contact pad and can be coupled to each resonator (64). A corresponding manufacturing method is also disclosed.

Inventors

• 칸탈루베 크리스토퍼 에이

Assignees

• 마이크로소프트 테크놀로지 라이센싱, 엘엘씨

Dates

Publication Date

20260512

Application Date

20210325

Priority Date

20200427

Claims (20)

1. In integrated circuits, A first substrate - the first substrate has a plurality of spaced-apart conductive contact pads on the surface of the first substrate -; A dielectric layer placed on the first substrate and the plurality of conductive contact pads; A second substrate placed on the dielectric layer above; and A plurality of superconducting contacts extending to the first substrate through the second substrate and the dielectric layer Includes, Each of the plurality of superconducting contacts is aligned with and in contact with each of the plurality of conductive contact pads, and is an integrated circuit.
2. An integrated circuit according to claim 1, wherein the dielectric layer is a thermosetting polymer.
3. An integrated circuit according to claim 1, wherein the first substrate is formed of silicon, glass, or a compound semiconductor, and the second substrate is formed of silicon, glass, or a compound semiconductor.
4. An integrated circuit according to claim 1, wherein the plurality of superconducting contacts are formed from one of aluminum, niobium, niobium titanium nitride, and niobium nitride.
5. An integrated circuit according to claim 1, further comprising a plurality of qubits disposed within the first substrate, wherein each of the plurality of conductive contact pads is coupled to each of the plurality of qubits.
6. An integrated circuit according to claim 5, further comprising a plurality of resonators disposed on the second substrate, wherein each of the plurality of superconducting contacts is coupled to each of the resonators of the plurality of resonators, and each of the resonators of the plurality of resonators is coupled to each of the qubits of the plurality of qubits.
7. As a method for forming an integrated circuit, Step of providing a first substrate - the first substrate has a plurality of conductive contact pads spaced apart from each other on the surface of the first substrate -; A step of placing a dielectric layer on the first substrate and the plurality of conductive contact pads; A step of placing a second substrate on the dielectric layer above; A step of forming a plurality of vias from the upper surface of the second substrate to the first substrate through the second substrate and the dielectric layer - each via extends to and is aligned with each conductive contact pad of the plurality of conductive contact pads -; and The method includes the step of filling the plurality of vias with a superconducting material and performing contact material filling to form a plurality of superconducting contacts extending to the first substrate through the second substrate and the dielectric layer, A method for forming an integrated circuit in which each of the plurality of superconducting contacts is aligned with and contacts each of the plurality of conductive contact pads.
8. A method for forming an integrated circuit according to claim 7, further comprising the step of heating the dielectric layer to bond the second substrate to the first substrate, wherein the dielectric layer is a thermosetting polymer.
9. In claim 7, the step of forming the plurality of vias is, A step of performing a first etching on the second substrate to form a plurality of TSV (through substrate via) openings on the second substrate; and A method for forming an integrated circuit, comprising the step of performing a second etching on the second substrate and the dielectric layer to provide an extended opening to the first substrate through the dielectric layer based on a mask pattern formed by the plurality of TSV openings of the second substrate.
10. A method for forming an integrated circuit according to claim 7, wherein the first substrate and the second substrate are both formed from silicon, glass, or a compound semiconductor.
11. A method for forming an integrated circuit according to claim 7, wherein the plurality of superconducting contacts are formed from one of aluminum, niobium, niobium titanium nitride, and niobium nitride.
12. A method for forming an integrated circuit according to claim 7, further comprising the step of manufacturing a plurality of qubits disposed within the first substrate, wherein each of the plurality of conductive contact pads is coupled to each of the qubits of the plurality of qubits.
13. A method for forming an integrated circuit according to claim 12, further comprising the step of manufacturing a plurality of resonators disposed on the second substrate, wherein each of the plurality of superconducting contacts is coupled to each of the resonators of the plurality of resonators, and each of the resonators of the plurality of resonators is coupled to each of the qubits of the plurality of qubits.
14. In claim 7, the step of forming the plurality of vias is, A step of performing a first etching on the dielectric layer to provide an extended via opening to the first substrate through the dielectric layer; and To form a plurality of TSV openings in the second substrate, a step of performing a second etching on the second substrate before the second substrate is disposed on the dielectric layer. Includes, A method for forming an integrated circuit, wherein the step of placing the second substrate on the dielectric layer comprises the step of placing the second substrate on the dielectric layer such that the plurality of TSV openings are aligned with the plurality of extended via openings to form a plurality of vias from the upper surface of the second substrate to the first substrate through the second substrate and the dielectric layer, and each via extends to and is aligned with each of the plurality of conductive contact pads.
15. As a method for forming an integrated circuit, Step of providing a first substrate - the first substrate has a plurality of conductive contact pads spaced apart from each other on the surface of the first substrate -; A step of placing a dielectric layer on the first substrate and the plurality of conductive contact pads; A step of performing a first etching on the dielectric layer to provide an extended via opening to the first substrate through the dielectric layer - each extended via opening is aligned with each conductive contact pad of the plurality of conductive contact pads -; A step of performing a second etching on a second substrate to form a plurality of TSV (through substrate via) openings on the second substrate; Step of placing the second substrate on the dielectric layer - the second substrate is placed on the dielectric layer before or after the second etching, and the plurality of TSV openings are aligned with a plurality of extended via openings to form a plurality of vias from the upper surface of the second substrate through the second substrate and the dielectric layer to the first substrate, and each via extends to and is aligned with each conductive contact pad of the plurality of conductive contact pads -; and The method includes the step of filling the plurality of vias with a superconducting material and performing contact material filling to form a plurality of superconducting contacts extending to the first substrate through the second substrate and the dielectric layer, A method for forming an integrated circuit in which each of the plurality of superconducting contacts is aligned with and in contact with each of the plurality of conductive contact pads.
16. A method for forming an integrated circuit according to claim 15, further comprising the step of heating the dielectric layer to bond the second substrate to the first substrate, wherein the dielectric layer is a thermosetting polymer.
17. A method for forming an integrated circuit according to claim 15, wherein the first substrate and the second substrate are both formed from silicon, glass, or a compound semiconductor.
18. A method for forming an integrated circuit according to claim 15, wherein the plurality of superconducting contacts are formed from one of aluminum, niobium, niobium titanium nitride, and niobium nitride.
19. A method for forming an integrated circuit according to claim 15, further comprising the step of manufacturing a plurality of qubits disposed within the first substrate, wherein each of the plurality of conductive contact pads is coupled to each of the plurality of qubits.
20. A method for forming an integrated circuit according to claim 19, further comprising the step of manufacturing a plurality of resonators disposed on the second substrate, wherein each of the plurality of superconducting contacts is coupled to each of the resonators of the plurality of resonators, and each of the resonators of the plurality of resonators is coupled to each of the qubits of the plurality of qubits.

Description

Bumpless Superconductor Device Related applications This application claims priority from U.S. patent application serial number 16/858812 filed on April 27, 2020, the entirety of which is incorporated herein. Technology field The present disclosure generally relates to integrated circuits, and more specifically to bumpless superconductor devices. High-density three-dimensional (3D) chip integration technology generally involves bonding two separate substrates/chips using a slight bump bonding variation. A bump is a raised metal pillar or sphere formed on the surface of a chip/substrate with a diameter of approximately 25–200 µm and a height of 10–200 µm. For bump bonding, the substrates to be bonded must be "bumped" with a suitable bonding metal (SnPb, SnAg, SnCu, In, etc.). Substrate bumping involves the patterning and deposition of a bump-under-metallization layer (e.g., Ti, TiW, Cr, Pd, Ni, etc.) acting as an adhesion promoter and/or diffusion barrier, followed by the plating of the aforementioned bonding metal. Once "bumped," the substrates or chips are bonded by precisely aligning the bumps and applying force, temperature, ultrasonic power, or a combination thereof to form a conductive metal joint between the two chips. Following this bonding process, it is standard practice to distribute a thermosetting polymer material (typically epoxy-based), referred to as underfill, between two bonding layers that function as a stress buffer and isolate the bump from the surrounding environment. The driving factors for lower power, lower latency, and higher interconnect density require inter-chip connections to have smaller diameters and tighter pitches. Advanced mass-production chip bumping used in High Bandwidth Memory (HBM) currently utilizes Cu-filler microbumps with a diameter of approximately 25 µm and a bump pitch of 55 µm. Beyond this stage, however, the actual cost of packaging integration limits the use of this technology primarily to the high-end segments of the GPU, NPU, and CPU markets. At these pitches and diameters, maintaining bump and bonding yields becomes difficult because the alignment and flatness of the bonding process must be precisely controlled to ensure that all bumps are bonded. Generally, this type of flip-chip bonding cannot be reworked. Furthermore, a side effect of reducing bump diameter is that the inter-chip spacing decreases because the reduced bump height limits the aspect ratio of the plating pillars. This increases the stress on the bumps, which is a function of stand-off height. In addition, there are additional constraints on underfill materials and underfill dispensing processes, as very precise liquid dispensing tools are required to ensure consistent underfill dispensing volumes and highly engineered low-viscosity materials must be developed to fill narrow gaps. In one example, an integrated circuit is provided, said integrated circuit comprises: a first substrate—said that the first substrate has a plurality of conductive contact pads spaced apart from each other on the surface of the first substrate—; a dielectric layer placed over the first substrate and the plurality of conductive contact pads; and a second substrate placed over the dielectric layer. A plurality of superconducting contacts extend to the first substrate through the second substrate and the dielectric layer, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and contacts each conductive contact pad of the plurality of conductive contact pads. In another example, a method for forming a superconducting device is disclosed. The method comprises the steps of: providing a first substrate—the first substrate has a plurality of spaced-apart conductive contact pads on the surface of the first substrate—; placing a dielectric layer on the first substrate and the plurality of conductive contact pads; and placing a second substrate on the dielectric layer. A plurality of vias are formed from the upper surface of the second substrate to the first substrate through the second substrate and the dielectric layer, and each via extends to and is aligned with each conductive contact pad of the plurality of conductive contact pads. The method further comprises the step of filling the plurality of vias with a superconducting material and performing contact material filling to form a plurality of superconducting contacts extending to the first substrate through the second substrate and the dielectric layer, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and contacts each conductive contact pad of the plurality of conductive contact pads. In another example, a method for forming an integrated circuit is disclosed. The method comprises the steps of: providing a first substrate—the first substrate has a plurality of spaced-apart conductive contact pads on the surface of the first substrate—; placing a dielectric layer on the first