KR-20260066156-A - Directed Refresh Management (DRFM) Address Capture in High Bandwidth Memory (HBM)

Abstract

Examples in this specification describe techniques for Directed Refresh Management (DRFM) address capture in High Bandwidth Memory (HBM). Some examples are based on an enable command containing a DRFM flag, including an example where an enable command is received and processed while a bank is open, an example where the address of a target row is captured without opening the corresponding bank, and an example where the address of a target row is captured based additionally on a mode register. Other examples are based on a precharge command containing a DRFM flag.

Inventors

• 리트 마이클
• 야오 유빈

Assignees

• 어드밴스드 마이크로 디바이시즈, 인코포레이티드
• 에이티아이 테크놀로지스 유엘씨

Dates

Publication Date

20260512

Application Date

20240618

Priority Date

20240617

Claims (15)

1. As an integrated circuit device, A high bandwidth memory (HBM) device comprising a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies comprise individual banks of memory cells and a control circuit, and the control circuit, Receiving an enable command directed to a bank of the above DRAM die—the enable command includes the address of a target row of memory cells within the bank and a directed refresh management (DRFM) flag field—and An integrated circuit device configured to capture the address of a target row of the memory cell when the above DRFM flag field is set.
2. In paragraph 1, the control circuit is, Open the bank based on the above activation command; While the above bank is open, receive a column command directed to the target row of the above memory cell; While the above bank is open, the column command is executed for the target row of the above memory cell; and An integrated circuit device further configured to close the bank based on a precharge command directed to the bank after performing the above-mentioned heat command.
3. In paragraph 1, the control circuit is, An integrated circuit device further configured to capture the address of a target row of the memory cell without opening the bank when the above DRFM flag field is set.
4. In paragraph 1, the control circuit is, An integrated circuit device further configured to perform a Directed Refresh Management (DRFM) event based on the captured address of a target row of the memory cell.
5. In paragraph 1, the control circuit is, An integrated circuit device further configured to receive the activation command while the bank is open.
6. In paragraph 1, the control circuit is, An integrated circuit device further configured to capture the address of a target row of the memory cell when the above DRFM flag is set and the mode register bit is set.
7. As an integrated circuit device, A high bandwidth memory (HBM) device comprising a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies comprise individual banks of memory cells and a control circuit, and the control circuit, Receive a precharge command directed to a bank of the above memory cells - the precharge command includes the address of a target row of the memory cells in the bank and a DRFM flag field -; An integrated circuit device configured to capture the address of a target row of a memory cell in a bank of memory cells when the above DRFM flag is set.
8. In paragraph 7, the above precharge order is, Multicycle precharge bank-specific instructions; and An integrated circuit device comprising one of the single-cycle precharge commands, wherein a pseudo-channel field of unit interval of the single-cycle precharge command serves as the DRFM flag field.
9. As a system, It includes a host device, and the host device is, Interfaces with a high bandwidth memory (HBM) device comprising a stack of dynamic random access memory (DRAM) dies—wherein the DRAM dies comprise individual banks of memory cells—and A system configured to issue a first activation command directed to a bank of the DRAM die, wherein the first activation command includes the address of the bank, the address of a target row of memory cells within the bank, and a directed refresh management (DRFM) flag field.
10. In paragraph 9, the host device is, Issue a first precharge command to close the above bank; After issuing the first precharge command, the first activation command is issued after a predetermined amount of time; and A system further configured to issue a second precharge command to close the bank after issuing the first precharge command.
11. In Clause 10, the above host device is, After issuing the first activation command above, issue a column command directed to the bank above; and A system further configured to issue the second precharge command after issuing the above heat command.
12. In Clause 10, the above host device is, A system further configured to issue the second precharge command to close the bank without issuing an intermediate column command directed to the target row of the memory cell after issuing the first precharge command.
13. In paragraph 9, the host device is, Issue the first activation command with the above DRFM flag field not set; and A system further configured to issue a second activation command directed to the bank while the bank is open, wherein the second activation command includes the address of a target row of the memory cell and the DRFM flag field, and wherein the DRFM flag field is set.
14. In paragraph 9, the host device is, A system further configured to issue a mode register command to the HBM device to set a mode register bit of the HBM device to signal that the address of a target row of the memory will be captured.
15. As a system, A host device configured to interface with a high-bandwidth memory (HBM) device comprising a stack of dynamic random access memory (DRAM) dies, wherein the DRAM dies comprise individual banks of memory cells, and the host device comprises It is configured to issue a precharge command directed to a bank of memory cells, wherein the precharge command includes the address of a target row of memory cells in the bank and a DRFM flag field, and the precharge command, Multicycle precharge bank-specific commands, and A system comprising one of the single-cycle precharge commands, wherein the pseudo-channel field of the unit interval of the single-cycle precharge command serves as the DRFM flag field.

Description

Directed Refresh Management (DRFM) Address Capture in High Bandwidth Memory (HBM) Examples of the present disclosure generally relate to directed refresh management (DRFM) address capture in high bandwidth memory (HBM). Many today's workloads and applications, such as AI, data analytics, video transcoding, and genomic analysis, require increasing amounts of memory bandwidth. Traditional Double Data Rate (DDR) memory solutions have been unable to keep up with growing compute demands, and memory bandwidth-intensive workloads are becoming bottlenecks for data movement and access. High Bandwidth Memory (HBM) helps alleviate these bottlenecks. HBM devices include multiple vertically stacked Dynamic Random Access Memory (DRAM) dies that can be mounted on a high-speed logic layer, along with a wide interface (e.g., a 1024-bit interface). The DRAM dies are connected to the high-speed logic layer via Through-Silicon Via (TSVs). HBM devices utilize an ultra-wideband (e.g., 1024-bit) interface architecture to provide high-bandwidth, high-speed, and low-power operation. The HBM standard is maintained by Committee JC-42.2 of JEDEC (Joint Electron Device Engineering Council), including the JEDEC standard JESD238. Directed Refresh Management (DRFM) is a process that refreshes memory rows requested by the host along with physically adjacent neighbor rows. DRFM is useful for countering Row Hammer (RH) phenomena, where a frequently active row (aggressor) causes a bit flip in an adjacent row (victim). RH can occur when the aggressor's activation rate exceeds the RH threshold (FlipTH). RH affects data integrity and can be exploited in various attack scenarios. DRFM is not available in current HBM devices and is not covered in the current HBM3 JEDEC standard. A technique for Directed Refresh Management (DRFM) address capture in High Bandwidth Memory (HBM) is described. One example is an integrated circuit device, which includes an HBM device having a stack of dynamic random access memory (DRAM) dies, and the DRAM dies include individual banks of memory cells and a control circuit, and the control circuit receives an enable command directed to a bank of DRAM dies—the enable command includes the address of a target row of memory cells within the bank and a DRFM flag field—and captures the address of a target row of memory cells if the DRFM flag field is set. Another example is an integrated circuit device including an HBM device having a stack of DRAM dies, wherein the DRAM dies include individual banks of memory cells and a control circuit, and the control circuit receives a precharge command directed to a bank of memory cells - the precharge command includes the address of a target row of memory cells in the bank and a DRFM flag field - and captures the address of a target row of memory cells in the bank of memory cells if the DRFM flag is set. Another example is a system including a host device, the host device interfaces with an HBM device including a stack of DRAM dies - the DRAM dies include individual banks of memory cells - and issues an enable command directed to a bank of DRAM dies, the enable command including the address of the bank, the address of a target row of memory cells within the bank and a DRFM flag field. More specific descriptions of the features cited above, briefly summarized above, may be provided with reference to exemplary implementations, some of which are illustrated in the accompanying drawings, so that the features cited above may be understood in detail. However, it should be noted that the accompanying drawings merely illustrate ordinary exemplary implementations and should not be construed as limiting the scope of the invention. FIG. 1 is a block diagram of an integrated circuit (IC) device including a high-bandwidth memory (HBM) having a stack of dynamic random access memory (DRAM) dies according to one example. Figure 2 is a block diagram of an HBM DRAM die stack according to one example. FIG. 3 illustrates a timing diagram of a row command and a column command for capturing a row address for a DRFM event based on the DRFM flag of an enable command according to one example. FIG. 4 illustrates a timing diagram of row commands and column commands for a situation in which a host decides to capture the row address of an open bank/row according to one example. FIG. 5 illustrates a timing diagram designed so that, according to one example, an HBM DRAM (e.g., a state machine of the HBM DRAM) processes an activation command including a DRFM flag (i.e., DRFM=1) set while the target bank/row is open, without needing to wait until the target bank/row is closed. FIG. 6 illustrates a timing diagram (600) designed so that the HBM DRAM processes an activation command (302) (i.e., when DRFM=1) while the target bank/row is open, as described above with reference to FIG. 5, according to one example, where the activation command (302) overlaps with a column command (404). FIG. 7 illustrates a timing diagram desi