KR-20260066220-A - MEMORY DEVICE INCLUDING GATE CAPPING LAYER

Abstract

According to embodiments of the present disclosure, a memory device may include a substrate including an active region, a word line embedded within the substrate and crossing the active region, a gate insulating layer surrounding the side and bottom surface of the word line, a gate capping layer disposed on the inner surface of the gate insulating layer on the word line, and a bit line contact in contact with the active region between the word line, the side facing the gate capping layer being concave toward the center.

Inventors

• 김성수
• 원나혜
• 김승희

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260512

Application Date

20241104

Claims (19)

1. A substrate including an active region; A word line embedded within the substrate and crossing the active region; A gate insulating layer surrounding the side and bottom surfaces of the above word line; A gate capping layer disposed on the inner surface of the gate insulating layer on the above word line; and A bit line contact that contacts the active region between the word lines, and whose side facing the gate capping layer is concave toward the center; A memory device including
2. In paragraph 1, It further includes a buffer layer disposed on the gate capping layer, and The above buffer layer is a memory device in contact with the upper surface of the above word line.
3. In paragraph 1, The above gate capping layer is a memory device that covers the entire upper surface of the above word line.
4. In paragraph 3, It further includes a buffer layer disposed on the gate capping layer, and A memory device in which the lowest surface of the above buffer layer contacts the gate capping layer in the region between the inner surfaces of the above gate capping layer.
5. In paragraph 4, It further includes a spacer surrounding the side of the bit line contact, and A memory device in which the outer surface of the above spacer contacts the buffer layer and the gate capping layer.
6. In paragraph 5, A memory device in which the lowest surface of the above buffer layer is located at a lower level than the lower surface of the above bit line contact.
7. In paragraph 1, The bit line contact above includes a first portion and a second portion located on the first portion and continuous with the first portion, A memory device in which the angle between the side of the first part and the upper surface of the substrate is different from the angle between the side of the second part and the upper surface of the substrate.
8. In paragraph 1, The bit line contact above includes a first portion and a second portion located on the first portion and continuous with the first portion, A memory device in which the upper surface area of the first part is smaller than the lower surface area of the second part.
9. In paragraph 1, A memory device in which the gate capping layer comprises a nitride and the buffer layer comprises an oxide.
10. A substrate including an active region; A word line embedded within the substrate and crossing the active region; A gate insulating layer surrounding the side and bottom surfaces of the above word line; A gate capping layer disposed on the inner surface of the gate insulating layer on the above word line; A buffer layer disposed on the gate capping layer and filling the space between the inner surfaces of the gate capping layer; and A bit line contact comprising a first portion contacting the active region between the word lines and a second portion located on the first portion and continuous with the first portion, wherein the angle formed by the side of the first portion with the upper surface of the substrate is different from the angle formed by the side of the second portion with the upper surface of the substrate; A memory device including
11. In Paragraph 10, A memory device in which the side of the bit line contact is concave toward the center of the bit line contact.
12. In Paragraph 11, The above buffer layer is a memory device in contact with the upper surface of the above word line.
13. In Paragraph 11, The above buffer layer is a memory device that fills the space between the inner surfaces of the gate capping layer.
14. In Paragraph 11, The above gate capping layer is a memory device that covers the entire upper surface of the above word line.
15. In Paragraph 11, A memory device in which the angle between the side of the first part and the upper surface of the substrate is greater than the angle between the side of the second part and the upper surface of the substrate.
16. In Paragraph 11, A memory device in which the upper surface area of the first part is smaller than the lower surface area of the second part.
17. A substrate including an active region; A bit line contact that contacts the active region, has a side that is concave toward the center, and includes a first portion and a second portion located on the first portion and continuous with the first portion; A gate capping layer located on the side of the first portion of the bit line contact; and A buffer layer located on the side of the second portion of the bit line contact; A memory device including
18. In Paragraph 17, A word line embedded within the substrate and crossing the active region; and It further includes a gate insulating layer surrounding the side and bottom surfaces of the above word line, and A memory device in which the gate capping layer is disposed on the inner surface of the gate insulating layer.
19. In Paragraph 17, The above buffer layer is a memory device that fills the space between the inner surfaces of the gate capping layer.

Description

Memory device including a gate capping layer The embodiments of the present disclosure relate to a memory device, and more specifically, to a memory device comprising a gate capping layer. Due to characteristics such as miniaturization, multifunctionality, and/or low manufacturing costs, memory devices are gaining prominence as a critical component in the electronics industry. As the electronics industry advances, memory devices are becoming increasingly highly integrated. To achieve this high integration, the linewidth of the wiring included in the memory devices is steadily decreasing, and the size of memory cells is shrinking. Consequently, the difficulty of the processes for forming memory cells is increasing. FIG. 1 is a drawing illustrating an example of a planar structure of a memory device according to embodiments of the present disclosure. Figure 2 is a drawing showing an example of the cross-sectional structure of the I-I' section of Figure 1. Figure 3a is an enlarged view of part 10 of Figure 2. Figure 3b is a drawing showing another example of part 10 of Figure 2. Figure 4 is a drawing showing an example of the cross-sectional structure of the II-II' section of Figure 1. Figure 5 is a drawing showing an example of the cross-sectional structure of the III-III' section of Figure 1. Figure 6 is a drawing showing another example of the cross-sectional structure of the I-I' section of Figure 1. Figure 7a is an enlarged view of section 20 of Figure 6. Figure 7b is a drawing showing another example of part 20 of Figure 6. Figure 8 is a drawing showing another example of the cross-sectional structure of the II-II' section of Figure 1. Figure 9 is a drawing showing another example of the cross-sectional structure of the III-III' section of Figure 1. FIGS. 10 to 16 are drawings illustrating examples of a method for forming a memory device according to embodiments of the present disclosure. FIGS. 17 to 20 are drawings illustrating other examples of a method for forming a memory device according to embodiments of the present disclosure. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the attached drawings, three directions parallel to the upper surface of the substrate are defined as the first direction (FD), the second direction (SD), and the third direction (TD), respectively, and a direction protruding perpendicularly from the upper surface of the substrate is defined as the fourth direction (VD). The first direction (FD) and the second direction (SD) may be substantially perpendicular to each other. The fourth direction (VD) is a direction perpendicular to the first direction (FD), the second direction (SD), and the third direction (TD). In the following specification, 'perpendicular' or 'perpendicular direction' will be used with substantially the same meaning as the fourth direction (VD). Directions indicated by arrows in the drawings and directions opposite thereto represent the same direction. FIG. 1 is a drawing illustrating an example of a planar structure of a memory device according to embodiments of the present disclosure. Referring to FIG. 1, a memory device according to embodiments of the present disclosure comprises an active region (110), a word line (120), a bit line structure (130), and a bit line contact (BLC). The word line (120) crosses the active region (110). The word line (120) extends in a first direction (FD). The word lines (120) are arranged parallel to each other in a second direction (SD). In one embodiment, two corresponding word lines (120) may cross one active region (110). The bit line structure (130) extends in a second direction (SD). The bit line structure (130) is arranged parallel to each other in a first direction (FD). The bit line structure (130) crosses the active area (110). The bit line structure (130) crosses the word line (120). The bit line structure (130) may be orthogonal to the word line (120). In one embodiment, one of the bit line structures (130) may cross one active area (110). Bit line contacts (BLCs) are positioned to overlap each active area (110). A bit line contact (BLC) may correspond to one active area (110). A bit line contact (BLC) may be located near the center of the active area (110). A bit line contact (BLC) is located between each word line (120). A bit line contact (BLC) overlaps each bit line structure (130) in the second direction (SD). In FIG. 1, the bit line contact is depicted as elliptical in a planar view, but the shape of the bit line contact is not limited thereto. FIG. 2 is a drawing showing an example of a cross-sectional structure along section I-I' of FIG. 1. FIG. 3a is an enlarged view of section 10 of FIG. 2. FIG. 3b is a drawing showing another example of section 10 of FIG. 2. FIG. 4 is a drawing showing an example of a cross-sectional structure along section II-II' of FIG. 1. Referring to FIGS. 2 to 4, a memory device according to embodiments