KR-20260066290-A - METHOD FOR FABRICATING BONDING STRUCTURE AND BONDING STRUCTURE FABRICATED USING THE SAME

KR20260066290AKR 20260066290 AKR20260066290 AKR 20260066290AKR-20260066290-A

Abstract

A method for manufacturing a bonding structure using a trimming process for a wafer bevel and a bonding structure manufactured using the same are provided. The method for manufacturing a bonding structure comprises providing a first substrate structure including a first semiconductor substrate having a first surface and a second surface opposite to each other and a first semiconductor device layer on the first surface, providing a second substrate structure including a second semiconductor substrate having a third surface and a fourth surface opposite to each other and a second semiconductor device layer on the third surface, removing a portion of the second semiconductor device layer disposed on a first edge region of the second semiconductor substrate, bonding the first substrate structure and the second substrate structure such that the first surface and the third surface face each other, forming a gap fill film that fills at least a portion of the gap between the first substrate structure and the first edge region, and after forming the gap fill film, performing a trimming process that removes at least a portion of the first edge region.

Inventors

임동찬
김석호
이호진
장주희

Assignees

삼성전자주식회사

Dates

Publication Date: 20260512
Application Date: 20241104

Claims (10)

A first substrate structure comprising a first semiconductor substrate including a first surface and a second surface opposite to each other, and a first semiconductor device layer on the first surface, is provided. A second substrate structure comprising a second semiconductor substrate including third and fourth surfaces opposite to each other, and a second semiconductor device layer on the third surface, is provided. A portion of the second semiconductor element layer disposed on the first edge region of the second semiconductor substrate is removed, and The first substrate structure and the second substrate structure are bonded so that the first surface and the third surface face each other, and A gap fill film is formed to fill at least a portion of the gap between the first substrate structure and the first edge region, and A method for manufacturing a bonding structure, comprising performing a trimming process to remove at least a portion of the first edge region after forming the gap fill film.
In Article 1, The method further includes removing a portion of the first semiconductor element layer disposed on the second edge region of the first semiconductor substrate, wherein A method for manufacturing a bonding structure, wherein the gap fill film fills at least a portion of the gap between the first edge region and the second edge region.
In Article 1, A method for manufacturing a bonding structure in which the coefficient of thermal expansion of the gap fill film is different from the coefficient of thermal expansion of the second semiconductor substrate.
In Article 1, A method for manufacturing a bonding structure, wherein removing a portion of the second semiconductor device layer comprises at least one of an Edge Exclusion Width (EEW) process, an Edge Bead Removal (EBR) process, or a Plasma Enhanced Strip (PES) process.
In Article 1, A method for manufacturing a bonding structure, wherein the above trimming process includes a laser trimming process.
In Article 1, A method for manufacturing a bonding structure, wherein the above trimming process includes a mechanical trimming process.
In Article 1, A method for manufacturing a bonding structure, further comprising, after performing the trimming process above, performing a thinning process to reduce the thickness of the second semiconductor substrate.
In Article 1, A method for manufacturing a bonding structure, wherein, after removing a portion of the second semiconductor element layer, the interior angle formed by the side of the second semiconductor element layer with respect to the third surface is an acute angle.
A first substrate structure comprising a first semiconductor substrate including a first surface and a second surface opposite to each other, and a first semiconductor device layer on the first surface, is provided. A second substrate structure comprising a second semiconductor substrate including third and fourth surfaces opposite to each other, and a second semiconductor device layer on the third surface, is provided. A portion of the second semiconductor element layer disposed on the first edge region of the second semiconductor substrate is removed, and The first substrate structure and the second substrate structure are bonded so that the first surface and the third surface face each other, thereby electrically connecting the first semiconductor device layer and the second semiconductor device layer. A gap fill film is formed to fill at least a portion of the gap between the first substrate structure and the first edge region, and After forming the gap filler film, a laser trimming process is performed to remove at least a portion of the first edge region, and After performing the laser trimming process described above, the method includes performing a thinning process to reduce the thickness of the second semiconductor substrate, wherein A method for manufacturing a bonding structure in which the coefficient of thermal expansion of the gap fill film is greater than the coefficient of thermal expansion of the second semiconductor substrate.
A first substrate structure comprising a first semiconductor substrate including a first surface and a second surface opposite to each other, and a first semiconductor device layer on the first surface, is provided. A portion of the first semiconductor element layer disposed on the first edge region of the first semiconductor substrate is removed, and A second substrate structure comprising a second semiconductor substrate including third and fourth surfaces opposite to each other, and a second semiconductor device layer on the third surface, is provided. A portion of the second semiconductor element layer disposed on the second edge region of the second semiconductor substrate is removed, and The first substrate structure and the second substrate structure are bonded so that the first surface and the third surface face each other, thereby electrically connecting the first semiconductor device layer and the second semiconductor device layer. A gap fill film is formed to fill at least a portion of the gap between the first edge region and the second edge region, and After forming the gap filler film, a trimming process is performed to remove at least a portion of the second edge region, and A method for manufacturing a bonding structure, comprising performing a thinning process to reduce the thickness of the second semiconductor substrate after performing the trimming process above.

Description

Method for fabricating a bonding structure and a bonding structure fabricated using the same The present invention relates to a method for manufacturing a bonding structure and a bonding structure manufactured using the same. More specifically, the present invention relates to a method for manufacturing a bonding structure using a trimming process for a wafer bevel and a bonding structure manufactured using the same. A semiconductor chip (semiconductor integrated circuit) can be manufactured on a semiconductor substrate (e.g., a wafer) through semiconductor manufacturing processes such as photolithography, etching, deposition, and ion implantation. As the thickness of the semiconductor chip decreases, the bevel, which is an inclined surface formed at the edge of the semiconductor substrate, causes non-uniform stress at the edge of the semiconductor substrate, resulting in defects such as cracks and/or delamination. Accordingly, a trimming process for the edge of the semiconductor substrate containing the bevel has been proposed. FIGS. 1 to 11 are intermediate step drawings for explaining a method for manufacturing a bonding structure according to some embodiments. FIGS. 12 to 15 are various intermediate step drawings for explaining a method of manufacturing a bonding structure according to some embodiments. FIGS. 16 and 17 are intermediate step drawings for explaining a method of manufacturing a bonding structure according to some embodiments. FIGS. 18 to 21 are intermediate step drawings for explaining a method for manufacturing a bonding structure according to some embodiments. FIGS. 22 to 24 are various intermediate step drawings for explaining a method of manufacturing a bonding structure according to some embodiments. Hereinafter, with reference to FIGS. 1 to 24, a method for manufacturing a bonding structure according to exemplary embodiments and a bonding structure manufactured using the same will be described. FIGS. 1 to 11 are intermediate step drawings for explaining a method for manufacturing a bonding structure according to some embodiments. For reference, FIG. 2 is an enlarged view for explaining the R1 region of FIG. 1, and FIG. 6 is an enlarged view for explaining the R2 region of FIG. 5. Referring to FIGS. 1 and FIGS. 2, a first substrate structure (100) is provided. The first substrate structure (100) may include a first semiconductor substrate (110) and a first semiconductor device layer (120). The first semiconductor substrate (110) may be, for example, bulk silicon or SOI (silicon-on-insulator). The first semiconductor substrate (110) may be a silicon substrate, or may include other materials, for example, silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first semiconductor substrate (110) may be one in which an epitaxial layer is formed on a base substrate. The first semiconductor substrate (110) may include a first surface (110a) and a second surface (110b) that are opposite to each other. The first surface (110a) may be an active surface on which a semiconductor device is formed. For example, the first surface (110a) may include a conductive region, for example, a well doped with impurities. Additionally, the first surface (110a) may have an insulating region, for example, various device isolation structures such as shallow trench isolation (STI). The first semiconductor substrate (110) may include a first center region (CR1) and a first edge region (ER1). The first edge region (ER1) may be defined along the perimeter of the first center region (CR1). That is, the first edge region (ER1) may be an edge portion of the first semiconductor substrate (110). The first edge region (ER1) may include a first bevel (BV1) having an incline with respect to the first surface (110a) and/or the second surface (110b). The first semiconductor device layer (120) may be formed on the first surface (110a) of the first semiconductor substrate (110). The first semiconductor device layer (120) may include various types of individual devices and/or interlayer insulating films. Individual devices may include various microelectronic devices, such as a MOSFET (metal-oxide-semiconductor field effect transistor) like a CMOS transistor (complementary metal-insulator-semiconductor transistor), a system LSI (large scale integration), a flash memory, a DRAM, an SRAM, an EEPROM, a PRAM, an MRAM, an RRAM, an image sensor like a CIS (CMOS imaging sensor), a micro-electro-mechanical system (MEMS), active devices, passive devices, etc., but are not limited thereto. In some embodiments, the first semiconductor element layer (120) may extend along at least a portion of the first bevel (BV1). The first semiconductor device layer (120) may include a circuit pattern (122), a wiring structure (124), and an insulating film (126) between the wirings. The circuit pattern (122) may include, for example, a transistor, but is