KR-20260066312-A - Method for forming fine line widths of RDL based on imprint process and RDL substrate manufactured thereby

KR20260066312AKR 20260066312 AKR20260066312 AKR 20260066312AKR-20260066312-A

Abstract

The present invention relates to a method for forming a fine line width of a redistribution circuit based on an imprint process and a redistribution circuit substrate produced thereby, comprising: a step of forming an imprint mold having an RDL pattern formed thereon using a photolithography process; b step of depositing an interlayer insulating layer on a base material and performing an imprint with the imprint mold; a step of removing the imprint mold to obtain an interlayer insulating layer having an RDL pattern trench formed thereon; c step of etching the RDL pattern trench to remove a residual film and adjusting the line width and spacing of the RDL pattern; a step of depositing a metal layer on top of the RDL pattern trench to form a metal electrode in the RDL pattern trench; and d step of polishing the top of the RDL pattern trench to remove the metal layer and expose the metal electrode. The present invention has the advantage of providing an imprint process-based method for forming fine line widths for rewiring that can connect lines to a chip at high density by resolving the lack of physical space in the section where a line bottleneck occurs at the part connected to the chip, and a rewiring substrate produced thereby.

Inventors

정성일
김판겸
하태규

Assignees

한국전기연구원

Dates

Publication Date: 20260512
Application Date: 20241104

Claims (16)

Step a of forming an imprint mold having an RDL pattern formed using a photolithography process; Step b, laminating an interlayer insulation layer onto a base material and performing an imprint with the imprint mold; A step of obtaining an interlayer insulation layer with an RDL pattern trench formed by removing an imprint mold; Step c, which involves etching the above RDL pattern trenches to remove the residual film and adjusting the RDL pattern line width and spacing; A step of forming a metal electrode in the RDL pattern trench by depositing a metal layer on top of the RDL pattern trench; and Step d, polishing the top of the RDL pattern trench to remove the metal layer and exposing the metal electrode to form an RDL wiring substrate; A method for forming fine line widths based on an imprint process, characterized by including
In paragraph 1, the above step a Step a1, sequentially stacking an exposure substrate, a photosensitive material, and a chrome mask having an RDL raw pattern formed thereon, and exposing to ultraviolet light; A step of obtaining a photosensitive pattern having an RDL raw pattern formed by developing after the above exposure; A step of obtaining a transparent phase mask by placing a transparent polymer on the above photosensitive pattern and removing the photosensitive pattern; A step of sequentially stacking a substrate, a metal layer, a phase exposure photosensitive material, and the phase mask, and phase-exposing to ultraviolet light; A step of obtaining a phase exposure photosensitive material pattern having an RDL molding pattern formed by developing after the above phase exposure; A step of forming a primary plating layer on the above-mentioned phase exposure photosensitive pattern and removing the phase exposure photosensitive pattern to obtain a primary plated specimen having an RDL molding pattern formed thereon; and A step of forming a second plating layer on the first plated specimen and removing the first plated specimen to obtain an imprint mold having an RDL molding pattern formed thereon; A method for forming fine line widths based on an imprint process, characterized by including
In paragraph 2 The above step a A method for forming a fine line width of a rewiring based on an imprint process, characterized by replacing the chrome mask in step a1 with the RDL wiring substrate obtained in step d.
In paragraph 1 The above step b The above interlayer insulation layer is formed by applying a liquid solution SOG (Spin on Glass) to a base material, and the step of forming an RDL pattern trench by imprinting the above imprint mold onto the SOG. A method for forming fine line widths based on an imprint process.
In paragraph 4, the above SOG is A method for forming fine line widths for rewiring based on an imprint process, characterized by being applied by a spin coating or spray coating method.
In paragraph 1, the above step c A method for forming fine line widths for redistribution based on an imprint process, characterized by the application of a wet etching, dry etching, or ICP RIE (Inductively Coupled Plasma Reactive Ion Etching) process.
In paragraph 6, the above wet etching process is A method for forming fine line widths for rewiring based on an imprint process, characterized by the use of a hydrogen fluoride (HF)-based wet etching process.
In paragraph 6, the above dry etching process is A method for forming fine line widths based on an imprint process, characterized by using a dry etching process based on a fluorocarbon-based gas (CF n) .
In Clause 7, the above ICP RIE process is Anisotropic etching is performed by simultaneously executing inhibitor deposition and etching using an etching gas composed of C and F, and A method for forming a fine line width through rewiring based on an imprint process, characterized by removing a residual film and adjusting the RDL pattern line width and spacing by controlling the content of C and F, the plasma source, and the bias power.
In paragraph 1, the above step c Before etching On the top of the interlayer insulation layer where an RDL pattern trench is formed A step of forming an etching mask that defines an etching protection portion; A method for forming fine line widths based on an imprint process, characterized by further including
In item 10, the above etching mask is Metal is deposited into the above RDL pattern trench using an oblique deposition process. A method for forming a fine line width for rewiring based on an imprint process, characterized by depositing a metal layer only in one direction of the above RDL pattern trench to protect it from etching, and allowing etching to be performed only in the other direction.
In item 10, the above step c A step of removing the etching mask after etching; A method for forming fine line widths based on an imprint process, characterized by including additional components.
In paragraph 1 A metal pad is formed on the base material of step b above. A method for forming a fine line width based on an imprint process, characterized by removing the residual film in step c above until the Metal Pad is exposed.
In paragraph 1 If the metal electrode is exposed in step d above, A method for forming a fine line width for rewiring based on an imprint process, characterized by additionally stacking an SOG on top and forming a UBM or Via hole pattern to connect with the metal electrode.
In paragraph 1 The imprint mold of step a above is fabricated in a range of line widths of 100 to 500 nm and line spacing of 1 to 2 μm, and A method for forming a fine line width for rewiring based on an imprint process, characterized by controlling the line width and line spacing to 1 μm or less through the etching process of step c above.
An imprint process-based rewiring substrate produced by any one of claims 1 to 15.

Description

Method for forming fine line widths of RDL based on imprint process and RDL substrate manufactured thereby The present invention relates to a method for forming fine line widths for rewiring based on an imprint process and a rewiring substrate produced thereby, and more specifically, to a technology that overcomes the physical limitations of wire bottleneck sections by proposing an RDL process that ultra-fineizes the wires formed on the substrate. The RDL (Re-Distribution Layer) is a technology in the semiconductor packaging process that facilitates external connections by rearranging pads on the chip surface. It plays a role in efficiently transmitting internal chip signals to the outside by forming a multilayer wiring structure at the wafer level. The cross-sectional structure of the RDL package includes a substrate (10) formed of a small metal plate connecting the chip and the external circuit, a metal pad (40), an ILD (Inter-Layer Dielectric) (30), an RDL (20), a UBM, or a via hole pattern (50), as shown in FIG. 1. Such RDL offers the advantages of minimizing chip area to fabricate smaller and lighter semiconductors, freely adjusting pad positions to implement various circuit shapes, making connections between pads more stable to extend the lifespan of the semiconductor, and increasing circuit integration density by placing more pads in a confined space. Accordingly, RDL is utilized in fields requiring high-density connectivity on the chip, such as wafer-level packaging (WLP), flip-chip, and fan-out WLP. To fabricate RDL, thin film formation technology is required to form a thin metal layer on the chip to create and connect new pads, and fine wire formation technology is required for high-density connections. However, as shown in Fig. 1b, as high-density connections are required on the chip, there is a technical problem where a line bottleneck (A) occurs at the connection point with the chip, resulting in a shortage of physical space. This is because, in the conventional method, the fabrication of RDL is carried out by photo-exposure using a chrome mask for forming RDL patterns, and there was a technical problem in that it was difficult to form the line width and spacing of the RDL pattern to less than 1 μm with such a photo-exposure process. FIG. 1a is a side cross-sectional structure of an embodiment of RDL, and FIG. 1b is a plan view of an embodiment of RDL. FIGS. 2 and FIGS. 3 are exemplary embodiments of the present invention. FIG. 4 is an exemplary illustration of applying SOG (Spin on Glass) to a base material. FIG. 5 is an exemplary diagram of the etching process of the present invention. FIG. 6 is an explanatory diagram of the etching mask formation and etching process of the present invention. FIG. 7 is an explanatory diagram of the fabrication of an etching mask according to the present invention. FIG. 8 is another exemplary embodiment of the present invention. FIG. 9 is another exemplary embodiment of step (S110) of the present invention. The present invention will be examined below with reference to the drawings. In describing the present invention, if it is determined that a detailed description of related known technologies or configurations may unnecessarily obscure the essence of the invention, such detailed description will be omitted. Furthermore, the terms described below are defined in consideration of their functions in the present invention; since these may vary depending on the intentions or practices of the user or operator, their definitions should be based on the content throughout this specification describing the present invention. Figure 1a below is a side cross-sectional structure of an embodiment of RDL, Figure 1b is a plan view of an embodiment of RDL, Figures 2 and 3 are exemplary diagrams of the present invention, Figure 4 is an exemplary diagram of applying SOG (Spin on Glass) to a substrate, Figure 6 is an explanatory diagram of the etching mask formation and etching process of the present invention, Figure 7 is an explanatory diagram of the etching mask fabrication of the present invention, Figure 8 is another exemplary diagram of the present invention, and Figure 9 is another exemplary diagram of a step (S110) of the present invention. The present invention relates to a method for forming fine line widths of rewiring based on an imprint process. Step a (S100) of the present invention is a step of forming an imprint mold (180') having an RDL pattern formed thereon using a photolithography process. Referring to FIG. 2 below, step a (S100) is performed as follows. The above photolithography process is a generally known method, wherein a step (S110) is performed in which an exposure substrate (100), a photosensitive material (110), and a chrome mask (120) having an RDL raw pattern formed thereon are sequentially stacked and exposed to ultraviolet light. In the next step (S120), the photosensitive pattern (110') formed by developing after the exposure is obtained, in wh