KR-20260066315-A - SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

Abstract

A semiconductor device with improved performance and reliability and an electronic system including the same are provided. A semiconductor device, wherein one aspect of the semiconductor device of the present invention for solving the problem comprises: a substrate; a device isolation film defining a first active region within the substrate; a first source/drain region having a first conductivity type and in contact with the device isolation film in a first direction within the first active region; a second source/drain region having a first conductivity type and spaced apart from the first source/drain region in a first direction within the first active region; a first gate electrode extending in a second direction intersecting the first direction on the first active region between the first source/drain region and the second source/drain region; a second gate electrode extending in a second direction on the first active region, wherein a second source/drain region is interposed between the first gate electrode and the second gate electrode; and a first auxiliary electrode on the device isolation film, wherein, in a planar view parallel to the upper surface of the substrate, the first auxiliary electrode does not overlap with the first source/drain region in the second direction and overlaps with the second source/drain region in the second direction.

Inventors

• 김동규
• 오준석
• 이세훈
• 장성필

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20241104

Claims (10)

1. Substrate; A device isolation film defining a first active region within the above substrate; A first source/drain region having a first conductivity type, in contact with the device isolation film in a first direction within the first active region; Within the first active region, a second source/drain region spaced apart from the first source/drain region in the first direction and having the first conductivity type; A first gate electrode extending in a second direction intersecting the first direction on the first active region between the first source/drain region and the second source/drain region; A second gate electrode extending in the second direction on the first active region, wherein the second source/drain region is interposed between the first gate electrode and the second gate electrode; and The device includes a first auxiliary electrode on the above-mentioned device separator, A semiconductor device in which, from a planar perspective parallel to the upper surface of the substrate, the first auxiliary electrode does not overlap with the first source/drain region in the second direction and overlaps with the second source/drain region in the second direction.
2. In Article 1, A semiconductor device in which a ground voltage is applied to the first auxiliary electrode.
3. In Article 1, A semiconductor device comprising, within the substrate, an impurity region surrounding the device isolation layer and having a second conductivity type different from the first conductivity type.
4. In Paragraph 3, A semiconductor device in which, from the above planar perspective, the first auxiliary electrode is interposed between the second source/drain region and the impurity region.
5. In Article 1, A semiconductor device in which the first gate electrode and the first auxiliary electrode are formed at the same level.
6. In Article 1, Within the first active region, a third source/drain region having the first conductivity type, spaced apart from the second source/drain region in the first direction, and Within the first active region, a fourth source/drain region spaced apart from the third source/drain region in the first direction, in contact with the device isolation film in the first direction, and having the first conductivity type, and On the first active region between the third source/drain region and the fourth source/drain region, a third gate electrode extending in the second direction, and The device further comprises a second auxiliary electrode on the above-mentioned device separator, A semiconductor device in which, from the above planar perspective, the second auxiliary electrode overlaps with the third source/drain region in the second direction and does not overlap with the fourth source/drain region in the second direction.
7. In Article 6, A semiconductor device in which the second auxiliary electrode is spaced apart from the first auxiliary electrode in the first direction.
8. Substrate; A device isolation film defining a first active region within the above substrate; A first source/drain region having a first conductivity type within the first active region; Within the first active region, a second source/drain region spaced apart from the first source/drain region in a first direction and having the first conductivity type; A first gate electrode extending in a second direction intersecting the first direction on the first active region between the first source/drain region and the second source/drain region; An auxiliary electrode on the above-mentioned device separator; and Within the above substrate, the device isolation layer is surrounded and includes an impurity region having a second conductivity type different from the first conductivity type, A semiconductor device in which the auxiliary electrode and the impurity region are electrically connected.
9. In Article 8, A semiconductor device in which a ground voltage is applied to the auxiliary electrode and the impurity region.
10. Main board; A semiconductor device comprising, on the main substrate above, a first substrate of a peripheral circuit area and a second substrate of a cell area; and A main controller electrically connected to the semiconductor device on the main board, wherein The above semiconductor device is, Within the first substrate, a device isolation film defining a first active region, and Within the first active region, a first source/drain region having a first conductivity type and in contact with the device isolation film in a first direction, and Within the first active region, a second source/drain region spaced apart from the first source/drain region in the first direction and having the first conductivity type, and On the first active region between the first source/drain region and the second source/drain region, a first gate electrode extending in a second direction intersecting the first direction, and A second gate electrode extending in the second direction on the first active region, wherein the second source/drain region is interposed between the second gate electrode and the first gate electrode, and The auxiliary electrode on the above-mentioned device separator, and, On the second substrate above, a plurality of word lines stacked in sequence, and On the second substrate, a channel structure intersecting the plurality of word lines, and It further includes a bit line connected to the above channel structure, and An electronic system in which, from a planar perspective parallel to the upper surface of the first substrate, the auxiliary electrode does not overlap with the first source/drain region in the second direction and overlaps with the second source/drain region in the second direction.

Description

Semiconductor device and electronic system including the same The present invention relates to a semiconductor device and an electronic system including the same. More specifically, the present invention relates to a semiconductor device including memory cells arranged in three dimensions and an electronic system including the same. Driven by the trend toward miniaturization and lightweighting of electronic products, the demand for high integration of semiconductor devices is increasing. As semiconductor devices become increasingly highly integrated, the size of the components included within them (e.g., transistors) also decreases, leading to the problem of leakage current. Therefore, it is necessary to control the leakage current of semiconductor devices to improve their performance and reliability. Meanwhile, in electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. FIG. 1 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. Figure 2 is a schematic cross-sectional view taken along A-A of Figure 1. Figure 3 is a schematic cross-sectional view taken along B-B of Figure 1. Figure 4 is a schematic cross-sectional view taken along C-C of Figure 1. Figure 5 is a schematic cross-sectional view taken along D-D of Figure 1. Figure 6 is an enlarged view to explain the R1 region of Figure 1. FIG. 7 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. Figure 8 is a schematic cross-sectional view taken along A-A of Figure 7. FIG. 9 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. Figure 10 is a schematic cross-sectional view taken along A-A of Figure 9. FIG. 11 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. FIG. 12 is a schematic cross-sectional view taken along A-A of FIG. 11. FIG. 13 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. FIG. 14 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. FIG. 15 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. Figure 16 is an enlarged view to explain the R2 region of Figure 15. FIG. 17 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. FIG. 18 is a schematic cross-sectional view taken along A-A of FIG. 17. Figure 19 is a schematic cross-sectional view taken along C-C of Figure 17. FIG. 20 is a schematic block diagram for illustrating a non-volatile memory device according to some embodiments of the present invention. FIG. 21 is a schematic cross-sectional view illustrating a non-volatile memory device according to some embodiments of the present invention. Figures 22 and 23 are various enlarged views to illustrate the R3 region of Figure 21. FIG. 24 is a schematic cross-sectional view illustrating a non-volatile memory device according to some embodiments of the present invention. Figure 25 is an enlarged view to explain the R4 region of Figure 24. FIGS. 26 to 33 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to some embodiments of the present invention. FIG. 34 is an exemplary block diagram for illustrating an electronic system according to some embodiments of the present invention. FIG. 35 is an exemplary perspective view for illustrating an electronic system according to some embodiments of the present invention. FIGS. 36 and 37 are various schematic cross-sectional views taken along I-I' of FIG. 35. Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. In this specification, although terms such as first, second, upper, and lower are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Accordingly, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention. Furthermore, it is understood that the lower element or component mentioned below may be the upper element or component w