KR-20260066348-A - SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Abstract

Embodiments of the present invention provide a semiconductor device capable of improving gate-induced drain leakage (GIDL) and a method for manufacturing the same. A semiconductor device according to the present embodiment may include a trench formed within a substrate; a first gate insulating layer covering the bottom surface and sidewalls of the trench; a first buried conductive layer filling the bottom of the trench on top of the first gate insulating layer; a second buried conductive layer comprising a conductive metal oxide on top of the first buried conductive layer; and a second gate insulating layer disposed between the second buried conductive layer and the first gate insulating layer.

Inventors

• 황성환

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260512

Application Date

20241104

Claims (20)

1. A trench formed within the substrate; A first gate insulating layer covering the bottom surface and side walls of the above trench; A first embedded conductive layer that fills the bottom of the trench on top of the first gate insulating layer; A second buried conductive layer comprising a conductive metal oxide on top of the first buried conductive layer; and A second gate insulating layer disposed between the second embedded conductive layer and the first gate insulating layer. A semiconductor device including
2. In paragraph 1, The above first buried conductive layer is a semiconductor device comprising a metal or a metal nitride.
3. In paragraph 1, A semiconductor device comprising a second embedded conductive layer having a stacked structure of a conductive metal oxide, a metal nitride, and polysilicon, or a stacked structure of a conductive metal oxide, a metal, and polysilicon.
4. In paragraph 1, The above conductive metal oxide is a semiconductor device comprising the same metal as the first buried conductive layer.
5. In paragraph 1, The above first buried conductive layer is a semiconductor device comprising titanium nitride.
6. In paragraph 1, The above conductive metal oxide is a semiconductor device comprising titanium oxide.
7. In paragraph 1, A semiconductor device comprising a silicon oxide second gate insulating layer.
8. In paragraph 1, A semiconductor device further comprising a pin region below the first buried conductive layer, wherein the upper surface and side walls of the pin region are covered by the first gate insulating layer.
9. In paragraph 1, A semiconductor device further comprising a gate capping layer that fills the remainder of the trench above the second buried conductive layer.
10. In paragraph 1, A semiconductor device further comprising first and second conductive regions within a substrate on both sides of the trench.
11. In paragraph 1, The above substrate includes a plurality of spaced-apart active regions, and The above trench is a semiconductor device disposed within each of the above active regions.
12. Step of forming a trench in a substrate; A step of forming a first gate insulating layer covering the bottom surface and side walls of the above trench; A step of forming a first buried conductive layer on top of the first gate insulating layer to fill the bottom of the trench; A step of forming an insulating oxide layer on top of the first buried conductive layer and the first gate insulating layer; A step of forming a second embedded conductive layer on top of the insulating oxide layer; and A step of replacing the insulating oxide layer interposed between the first buried conductive layer and the second buried conductive layer with a conductive metal oxide, and performing heat treatment to form the insulating oxide layer interposed between the first gate insulating layer and the second buried conductive layer into a second gate insulating layer. A method for manufacturing a semiconductor device including
13. In Paragraph 12, The step of forming the insulating oxide layer above is, Method for manufacturing a semiconductor device using a plasma oxidation process.
14. In Paragraph 12, The step of forming the insulating oxide layer above is, A method for manufacturing a semiconductor device by proceeding with an oxide deposition process, a radical oxidation process, or an ion implantation process.
15. In Paragraph 12, A method for manufacturing a semiconductor device in which the first buried conductive layer comprises a metal or a metal nitride.
16. In Paragraph 12, A method for manufacturing a semiconductor device in which the first buried conductive layer comprises titanium nitride.
17. In Paragraph 12, The step of forming the second buried conductive layer is, A step of forming a metal or metal nitride that gap-fills a portion of the trench on top of the insulating oxide layer; A step of forming a polysilicon layer that gap-fills the trench on top of the metal or metal nitride; and A method for manufacturing a semiconductor device comprising the step of etching the polysilicon layer to gap-fill a portion of the trench.
18. In Paragraph 17, The step of performing the above heat treatment is, A method for manufacturing a semiconductor device, performed after the step of forming the metal or metal nitride and before the step of forming the polysilicon layer.
19. In Paragraph 17, The step of performing the above heat treatment is, A method for manufacturing a semiconductor device, performed after the step of forming the polysilicon layer and before the step of etching the polysilicon layer to gap-fill a portion of the trench.
20. In Paragraph 17, The step of performing the above heat treatment is, A method for manufacturing a semiconductor device performed after the step of etching the polysilicon layer to gap-fill a portion of the trench.

Description

Semiconductor Device and Method for Fabricating the Same The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a buried gate and a method for manufacturing the same. Metal gate electrodes are applied to achieve high performance in transistors. In particular, in buried gate type transistors, control of the threshold voltage is required for high-performance operation. Additionally, while Gate Induced Drain Leakage (GIDL) characteristics significantly affect the performance of buried gate type transistors, it is difficult to improve GIDL characteristics as semiconductor devices become more integrated. FIGS. 1a to 1c are plan and cross-sectional views illustrating a semiconductor device according to the embodiments of the present invention. FIGS. 2a to 2g are process cross-sectional views for explaining an example of a method for manufacturing a semiconductor device according to the present embodiment. FIGS. 3a to 3g are process cross-sectional views for explaining other examples of a semiconductor device manufacturing method according to the present embodiment. FIGS. 4a to 4h are process cross-sectional views for explaining another example of a method for manufacturing a semiconductor device according to the present embodiment. FIGS. 5A and FIGS. 5B are a plan view and a cross-sectional view illustrating another example of a semiconductor device of the present embodiment. The embodiments described herein will be explained with reference to cross-sectional, plan, and block drawings, which are ideal schematic diagrams of the invention. Accordingly, the shapes of the illustrative drawings may be modified by manufacturing techniques and/or tolerances, etc. Accordingly, the embodiments of the invention are not limited to the specific shapes depicted but include variations in shape produced according to the manufacturing process. Accordingly, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions illustrated in the drawings are intended to illustrate specific forms of the regions of the element and are not intended to limit the scope of the invention. The sizes and relative sizes of the components shown in the drawings may be exaggerated for clarity of description. Throughout the specification, the same reference numerals refer to the same components, and "and/or" includes each of the mentioned items and all combinations of one or more. When elements or a layer are referred to as being "on" or "on" another element or layer, this includes not only being directly on top of the other element or layer but also cases where another layer or element is interposed in between. The terms used herein are for describing the embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. FIGS. 1a to 1c are plan and cross-sectional views illustrating another example of a semiconductor device of the present embodiment. FIG. 1a is a plan view illustrating another example of a semiconductor device of the present embodiment. FIG. 1b is a cross-sectional view crossing FIG. 1a along the line A-A'. FIG. 1c is a cross-sectional view crossing FIG. 5a along the line B-B'. As illustrated in FIGS. 1a to 1c, a semiconductor device (100) may include a substrate (101) and a buried gate structure (100G) embedded in the substrate (101), a first doping region (120), and a second doping region (121). The buried gate structure (100G) and the first and second conductive regions (120, 121) may be cell transistors. The cell transistors can improve the short-channel effect due to the buried gate structure. The semiconductor device (100) may be part of a memory cell. For example, the semiconductor device (100) may be part of a memory cell of a DRAM. The semiconductor device (100) may include a bit line (BL) and a memory storage element (CAP) electrically connected to a substrate (101). A bit line (BL) can be electrically connected to a first doping region (120), and a memory storage element (CAP) can be electrically connected to a second doping region (121). A bit line (BL) can be electrically connected to the first doping region (120) through a bit line node (130), and a memory storage element (CAP) can be electrically connected to the second doping region (121) through a storage node (131). A bit line (BL) and a memory storage element (CAP) can be located at a higher level than the buried gate structure (100G). A bit line (BL) and a memory storage element (CAP) can be located at different levels. A memory storage element (CAP) can be located at a higher level than a bit line (BL). A memory storage element (CAP) may include a capacitor. The substrate (101) may be a material suitable for semiconductor processing. The substrate (101) may include a semiconductor substrate. The substrate (101) may be made of a