KR-20260066368-A - MEMORY APPARATUS

Abstract

A memory device according to an embodiment of the present invention may include a timing control circuit that outputs a system domain reset signal and a data domain reset signal having different output timings based on a system clock, and outputs the system clock as an internal clock when the system domain reset signal is output, and a domain crossing circuit that includes a plurality of first flip-flops operating based on the internal clock and a plurality of second flip-flops operating based on the data clock, wherein the plurality of first flip-flops are initialized by the system domain reset signal and the plurality of second flip-flops are initialized by the data domain reset signal.

Inventors

• 최종혁
• 윤상식
• 도형록
• 박정제
• 박준홍

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260512

Application Date

20241104

Claims (16)

1. A timing control circuit that outputs a system domain reset signal and a data domain reset signal with different output timings based on a system clock, and outputs the system clock as an internal clock when the system domain reset signal is output; and A domain crossing circuit comprising a plurality of first flip-flops operating based on the internal clock and a plurality of second flip-flops operating based on the data clock, wherein the plurality of first flip-flops are initialized by the system domain reset signal and the plurality of second flip-flops are initialized by the data domain reset signal. Memory device.
2. In paragraph 1, The above domain crossing circuit is, Pipe operation time required from the reception of the internal clock until the reception of the data clock. Memory device.
3. In paragraph 2, The above timing control circuit is, The output timing of the system domain reset signal is set to be faster than the output timing of the data domain reset signal. Memory device.
4. In paragraph 3, The above timing control circuit is, The output timing of the system domain reset signal is set faster than the toggle timing of the data clock by the pipe operation time. Memory device.
5. In paragraph 4, The above timing control circuit is, Delaying the system domain reset signal to generate the data domain reset signal Memory device.
6. In paragraph 5, The above timing control circuit is, Delaying the CAS command by a first set period of the system clock to generate the system domain reset signal, and The system domain reset signal is delayed by a second set period of the system clock to generate the data domain reset signal. Memory device.
7. In paragraph 1, The above domain crossing circuit is, A plurality of pipe circuits further comprising converting a command based on the system clock into a command based on the data clock based on the outputs of the plurality of first flip-flops and the plurality of second flip-flops. Memory device.
8. In Paragraph 7, The system domain reset signal is input to the set terminal of one of the plurality of first flip-flops, and The system domain reset signal is input to the reset terminals of the remaining flip-flops among the plurality of first flip-flops. Memory device.
9. In paragraph 8, The data domain reset signal is input to the set terminal of one of the plurality of second flip-flops, and The data domain reset signal is input to the reset terminals of the remaining flip-flops among the plurality of second flip-flops. Memory device.
10. In Paragraph 9, The initialization of the plurality of first flip-flops and the initialization of the plurality of second flip-flops are, A flip-flop receiving the system domain reset signal or the data domain reset signal at the set terminal outputs a level different from the remaining flip-flops. Memory device.
11. In Paragraph 10, The input/output structure of the plurality of first flip-flops and the plurality of second flip-flops is a ring structure. Memory device.
12. A command decoding circuit that outputs read-write commands and counter-commands synchronized with the system clock; A timing control circuit that outputs a system domain reset signal, a data domain reset signal, and an internal clock based on the CAS command and the system clock, and outputs a delayed Read Write command based on the system clock and the Read Write command; and A domain crossing circuit that outputs the delayed write read command as a data input/output command by synchronizing it with the data clock according to the control of the system domain reset signal, the data domain reset signal, and the internal clock. Memory device.
13. In Paragraph 12, The above timing control circuit is, Outputting the output of the above system domain reset signal at a timing faster than the above data domain reset signal Memory device.
14. In Paragraph 13, The above timing control circuit is, Outputting the system domain reset signal based on the above CAS command and the above system clock, outputting the system clock as the internal clock when the system domain reset signal is output, and delaying the system domain reset signal to output the data domain reset signal. Memory device.
15. In Paragraph 14, The above domain crossing circuit is, The reception timing of the internal clock is faster than the data clock. Memory device.
16. In paragraph 15, The above domain crossing circuit is, Receiving the data clock that toggles after the internal clock is received and the pipe operation time has elapsed Memory device.

Description

Memory Apparatus The present invention relates to integrated circuit technology and to a memory device. Recently, due to the miniaturization, low power consumption, high performance, and diversification of electronic devices, there is a demand for memory devices capable of storing information in various electronic devices, such as computers and portable communication devices. To achieve high performance, memory devices capable of high-speed data input and output are being developed to utilize a system clock for receiving addresses and commands and a data clock for input and output data. As such, memory devices utilizing heterogeneous clocks require a domain crossing circuit capable of synchronizing these heterogeneous clocks. For example, a domain crossing circuit is required to synchronize a command synchronized with the system clock with the data clock. FIG. 1 is a drawing for explaining the configuration of a memory device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating the configuration of a timing control circuit included in a memory device according to an embodiment of the present invention. FIG. 3 is a diagram illustrating the configuration of a domain crossing circuit included in a memory device according to an embodiment of the present invention. FIG. 4 is a timing diagram for explaining the operation of a memory device according to an embodiment of the present invention. FIG. 5 is a diagram illustrating the configuration of a memory device according to another embodiment of the present invention. FIG. 6 is a diagram illustrating the configuration of a timing control circuit included in a memory device according to another embodiment of the present invention. FIG. 7 is a diagram illustrating the configuration of a domain crossing circuit included in a memory device according to another embodiment of the present invention. FIG. 8 is a timing diagram for explaining the operation of a memory device according to another embodiment of the present invention. Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings. A memory device may be configured to store data and output stored data. For example, the memory device may receive a command from an external device (e.g., a memory controller) to store data or output stored data, and may receive data from the external device or output data stored in the external device. In this case, the memory device may receive the command synchronized with the system clock and output the stored data synchronized with the data clock. Accordingly, the memory device may include a domain crossing circuit for the system clock and the data clock. The following description relates to a domain crossing circuit included in a memory device utilizing heterogeneous clocks. It should be noted that this description describes a domain crossing circuit for a system clock and a data clock as an example of heterogeneous clocks, and is not limited to only the system clock and the data clock. FIG. 1 is a drawing for explaining the configuration of a memory device according to an embodiment of the present invention. Referring to FIG. 1, a memory device according to an embodiment of the present invention may include a command receiving circuit (10), a system clock receiving circuit (20), a data clock receiving circuit (30), a command decoding circuit (40), a timing control circuit (50), a domain crossing circuit (60), and a data input/output circuit (70). A command receiving circuit (10) can receive a signal (not shown) for controlling the operation of a memory device via a pad (PAD) from an external device (e.g., a memory controller) and output it as a command signal (CMD). At this time, the signal provided to the command receiving circuit (10) from the external device may be a single-ended signal or a differential-mode signal. Additionally, the command signal (CMD) output from the command receiving circuit (10) may be provided to a command decoding circuit (40). The system clock receiving circuit (20) can receive a signal (not shown) from an external device via a pad (PAD) to synchronize the operation of the memory device and the operation of an external device (e.g., a memory controller), and output it as a system clock (CLK). At this time, the signal provided to the system clock receiving circuit (20) from the external device may be a single-ended signal or a differential-mode signal. Additionally, the system clock (CLK) output from the system clock receiving circuit (20) may be provided to a command decoding circuit (40) and a timing control circuit (50). The data clock receiving circuit (30) can be enabled or disabled based on a CAS command (CAS_CMD). The enabled data clock receiving circuit (30) can receive a signal (not shown) from an external device via a pad (PAD) to synchronize the data input/output timing of the memory device with the data input/output timing o