KR-20260066379-A - POLISHING DEVICE FOR SEMICONDUCTOR WAFER

KR20260066379AKR 20260066379 AKR20260066379 AKR 20260066379AKR-20260066379-A

Abstract

The present invention relates to a semiconductor wafer polishing device for collecting impurities generated from a polishing pad that polishes the surface of a semiconductor wafer, comprising: a rotatable polishing plate portion to which a polishing pad for polishing the wafer is detachably mounted; a rotatable polishing portion that fixes the wafer in a state facing the polishing pad; a rotatable conditioning portion to which a disc for conditioning the polishing pad is detachably mounted; a supply portion that supplies a solution to the surface of the polishing pad; and a suction portion that collects impurities generated during the conditioning process of the polishing pad. The semiconductor wafer polishing device may include a suction portion to collect impurities generated during the conditioning process of the polishing pad.

Inventors

임대현
추정선
서건식
전은돈

Assignees

케이피엑스일렉트로켐 주식회사

Dates

Publication Date: 20260512
Application Date: 20241104

Claims (10)

In a semiconductor wafer polishing device for collecting impurities generated from a polishing pad that polishes the surface of a semiconductor wafer, A polishing pad for polishing the wafer is detachably mounted, and a rotatable plate is provided; A rotatable polishing part that fixes a wafer in a state facing the polishing pad; A disc for conditioning the above-mentioned polishing pad is detachably mounted, and a rotatable conditioning part; A supply unit for supplying a solution to the surface of the polishing pad; and A semiconductor wafer polishing device comprising: a suction unit for collecting impurities generated during the conditioning process of the polishing pad.
In claim 1, A semiconductor wafer polishing device characterized in that the above-mentioned suction part is spaced apart from the polishing pad and the wafer.
In claim 1, A semiconductor wafer polishing device characterized by the above suction part including a first suction part positioned facing a polishing pad and a second suction part positioned below a polishing plate.
In claim 3, The above first suction part A suction member for sucking in impurities; and A semiconductor wafer polishing device characterized by including a distance adjusting member for adjusting the distance between the suction member and the polishing pad.
In claim 3, A semiconductor wafer polishing device characterized by the first suction part sucking impurities at a vacuum level of 2,000 mmH₂O to 4,000 mmH₂O .
In claim 3, The above-mentioned second suction part surrounds the outer surface of the base plate, and A semiconductor wafer polishing device characterized in that the area of the second suction part is larger than the area of the polishing plate.
In claim 3, The above-mentioned second suction part and the surface part are circular in shape, sharing the same center, and A semiconductor wafer polishing device characterized in that the diameter of the second suction part is larger than the diameter of the polishing plate.
In claim 3, A semiconductor wafer polishing device characterized by the second suction part being inclined from the outer part toward the central part.
A method for collecting impurities using a semiconductor wafer polishing device according to claim 1, (1) A step of polishing a wafer by rotating the polishing pad mounted on the polishing plate and the wafer mounted on the polishing plate into contact; (2) A step of conditioning the polishing pad by rotating the polishing pad in contact with the wafer above with a disk mounted on the conditioning part; and (3) A step of collecting impurities generated during the above conditioning process using a suction part; a method for collecting impurities.
In claim 9, A method for collecting impurities characterized by the above (2) step being performed after the (1) step is completed.

Description

Polishing Device for Semiconductor Wafer The present invention relates to a semiconductor wafer polishing apparatus. Specifically, it relates to a semiconductor wafer polishing apparatus for collecting impurities generated from a polishing pad that polishes the surface of a semiconductor wafer, and a method for collecting impurities using the same. Chemical mechanical planarization (CMP) is a process in which a wafer attached to a polishing unit is in contact with a polishing pad attached to a polishing unit, and a slurry is supplied to chemically react the wafer surface while moving the wafer and the polishing pad relative to each other, thereby mechanically flattening the uneven parts of the wafer surface. Polishing pads are essential materials in the CMP process described above. They are generally composed of polyurethane-based resins and feature grooves on their surface that facilitate large slurry flow and pores that support fine flow. In particular, the slurry flow rate and the resulting polishing quality vary depending on the size and distribution of the pores. Generally, the smaller the pore size and the more uniform the distribution, the better the polishing characteristics achieved in the CMP process. However, during the polishing process, impurities including by-products such as metal oxides generated by wafer planarization and slurry residues remain on the polishing pad. In order to easily remove these impurities, a polishing pad conditioning process is performed together with or separately from the polishing process, in which ultrapure water is supplied to the surface of the polishing pad and the surface of the polishing pad is scrubbed with a disc. In the case of existing semiconductor wafer polishing devices, there was no suction part to collect the impurities, making it difficult to analyze impurities generated from the polishing pad during the conditioning process. Accordingly, the inventors completed the present invention after continuous research on a semiconductor wafer polishing device comprising a suction unit for collecting impurities generated from a polishing pad during the process of conditioning the polishing pad. FIG. 1 is a drawing showing a semiconductor wafer polishing apparatus according to one embodiment of the present invention viewed from the front. FIG. 2 is a drawing illustrating a semiconductor wafer polishing apparatus according to one embodiment of the present invention. FIG. 3 is a top view of a semiconductor wafer polishing apparatus according to one embodiment of the present invention. FIG. 4 is a flowchart of a method for collecting impurities using a semiconductor wafer polishing apparatus according to one embodiment of the present invention. The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the present invention, and the present invention is defined only by the scope of the claims. The terms used in this specification are for describing embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. The terms "comprises" and/or "comprising" used in this specification do not exclude the presence or addition of one or more other components in addition to the components mentioned. Throughout the specification, the same reference numerals refer to the same components, and "and/or" includes each of the mentioned components and all combinations of one or more. Although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical scope of the invention. Unless otherwise defined, all terms used herein (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which the present invention pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise. In this specification, directions such as front, back, up, down, left, and right that specify relative positions are intended to aid in understanding the invention, and unless otherwise specifically defined, the directions shown in the drawings are used as the reference. In this specification, “upper,” “top,” and “upper direction” refer to the Z-axis direction in the drawings, an