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KR-20260066403-A - MEMORY DEVICE COMPRISING NEAR-MEMORY PROCESSING UNIT AND MEMORY MANAGEMENT METHOD PERFORMED BY THE MEMORY DEVICE

KR20260066403AKR 20260066403 AKR20260066403 AKR 20260066403AKR-20260066403-A

Abstract

A memory device comprises a memory for storing instructions; and at least one processing unit including a processing circuit, wherein the memory device is connected to a host processor through an interface, and when the instructions are executed individually or collectively by the at least one processing unit, the memory device may be configured to select a candidate hot memory block based on the number of accesses counted for each of a plurality of memory blocks stored in the memory, select a hot sub-block based on the number of accesses counted for each of a plurality of sub-blocks divided from the selected candidate hot memory block, and transmit the hot sub-block to the host processor based on a memory instruction regarding the hot sub-block received from the host processor.

Inventors

  • 막심오스타펜코
  • 오덕재
  • 남지훈

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260512
Application Date
20241104

Claims (20)

  1. In a memory device, Memory for storing instructions; and At least one processing unit including a processing circuit Includes, The above memory device is, Connected to the host processor through the interface, and When the above instructions are executed individually or collectively by the at least one processing unit, the memory device, Based on the number of accesses counted for each of the plurality of memory blocks stored in the memory above, a candidate hot memory block is selected, and A hot sub-block is selected based on the number of accesses counted for each of the plurality of sub-blocks divided from the above-mentioned selected candidate hot memory block, and Based on a memory instruction regarding the hot sub-block received from the host processor, the hot sub-block is transmitted to the host processor. making, Memory device.
  2. In paragraph 1, When the above instructions are executed by the processing unit, the memory device, Among the plurality of memory blocks above, one or more memory blocks having an access count greater than or equal to a first threshold access count are selected as the candidate hot memory blocks, and Each of the above-mentioned selected candidate hot memory blocks is divided into multiple sub-blocks, and Among the above-mentioned plurality of divided sub-blocks, a sub-block having an access count greater than or equal to a second threshold access count is selected as the hot sub-block. making, Memory device.
  3. In paragraph 1, When the above instructions are executed by the processing unit, the memory device, During a first time range, count the number of accesses to each of the plurality of memory blocks, and Counting the number of accesses to each of the plurality of sub-blocks during a second time range following the first time range. making, Memory device.
  4. In paragraph 3, The first threshold access count for selecting the above candidate hot memory block is, Determined based on the ratio of the time length of the first time range to the time length of the period including the first time range and the second time range. Memory device.
  5. In paragraph 1, The size of the memory block is, Larger than the size of the sub-block, Memory device.
  6. In paragraph 1, The above memory is, It further includes a hot buffer, When the above instructions are executed by the processing unit, the memory device, The address of the selected hot sub-block is stored in the hot buffer, and Based on the fact that the host processor accessed the hot buffer, it receives a read command for the hot sub-block, and Based on the above read command, transmit the hot sub-block to the host processor. To do so, The hot sub-block among the above memories is, After being transmitted to the host processor, it is deallocated by the host processor, Memory device.
  7. In paragraph 6, The above host processor is, Accessing the hot buffer of the memory device using MMIO (memory-mapped input/output), Memory device.
  8. In paragraph 6, When the above instructions are executed by the processing unit, the memory device, After transmitting the above hot sub-block to the host processor, delete the address of the hot sub-block stored in the hot buffer. making, Memory device.
  9. In paragraph 1, The above memory device is, It includes a secondary memory device, The above hot sub-block is, After the information regarding the above hot sub-block is transmitted to the host processor, it is stored in the main memory device of the host processor. Memory device.
  10. In paragraph 1, The above memory is, It includes a first memory zone and a second memory zone, and When the above instructions are executed by the processing unit, the memory device, Among the plurality of memory blocks stored in the first memory zone, one or more memory blocks having an access count less than or equal to a threshold access count are merged into a super block, and Configure the above merged super block as the above second memory zone, and Restricting the counting of accesses to the aforementioned merged super block making, Memory device.
  11. In paragraph 1, The above memory is, It includes a first memory zone and a second memory zone, and When the above instructions are executed by the processing unit, the memory device, Based on the occurrence of access to the super block stored in the second memory zone, memory blocks are obtained by dividing the accessed super block, and The memory blocks obtained through the above division are configured as the first memory zone, and Counting the number of accesses to memory blocks obtained through the above partitioning making, Memory device.
  12. In a memory management method performed by a memory device, A step of selecting a candidate hot memory block based on the number of accesses counted for each of the plurality of memory blocks stored in the memory of the memory device; A step of selecting a hot sub-block based on the number of accesses counted for each of the plurality of sub-blocks divided from the selected candidate hot memory block; and A step of transmitting the hot sub-block to the host processor based on a memory instruction regarding the hot sub-block received from the host processor. A memory management method including
  13. In Paragraph 12, The step of selecting the above candidate hot memory block is, Among the plurality of memory blocks, the method includes the step of selecting one or more memory blocks having an access count greater than or equal to a first threshold access count as the candidate hot memory blocks. The step of selecting the above hot sub-block is, A step of dividing each of the above-mentioned selected candidate hot memory blocks into a plurality of sub-blocks; and Among the above-described plurality of sub-blocks, the step of selecting a sub-block having an access count greater than or equal to a second threshold access count as the hot sub-block, Memory management methods.
  14. In Paragraph 12, The step of selecting the above candidate hot memory block is, The method includes the step of counting the number of accesses to each of the plurality of memory blocks during a first time range, and The step of selecting the above hot sub-block is, A method comprising the step of counting the number of accesses to each of the plurality of sub-blocks during a second time range following the first time range. Memory management methods.
  15. In Paragraph 12, The above memory management method is, The method further includes the step of storing the address of the selected hot sub-block in the hot buffer of the memory device. The step of transmitting the above hot sub-block to the host processor is, Based on the fact that the host processor has accessed the hot buffer, the step of receiving a read command for the hot sub-block; and Based on the above read command, the method includes the step of transmitting the hot sub-block to the host processor, The hot sub-block among the above memories is, After being transmitted to the host processor, it is deallocated by the host processor, Memory management methods.
  16. In paragraph 15, The above memory management method is, The method further comprises the step of deleting the address of the hot sub-block stored in the hot buffer after transmitting the hot sub-block to the host processor. Memory management methods.
  17. In Paragraph 12, The above memory device is, It includes a secondary memory device, The above hot sub-block is, After the information regarding the above hot sub-block is transmitted to the host processor, it is stored in the main memory device of the host processor. Memory management methods.
  18. In Paragraph 12, The memory of the above memory device is, It includes a first memory zone and a second memory zone, and The above memory management method is, A step of merging one or more memory blocks having an access count less than or equal to a threshold access count among the plurality of memory blocks stored in the first memory zone into a super block; A step of configuring the merged super block as the second memory zone; and A further step of limiting the number of accesses to the merged super block, Memory management methods.
  19. In Paragraph 12, The memory of the above memory device is, It includes a first memory zone and a second memory zone, and The above memory management method is, A step of acquiring memory blocks by dividing the accessed super block based on the occurrence of access to the super block stored in the second memory zone; A step of configuring the memory blocks obtained through the above division into the first memory zone; and A method comprising the step of counting the number of accesses to memory blocks obtained through the above partitioning, Memory management methods.
  20. A computer-readable recording medium storing one or more computer programs comprising instructions for performing the method of any one of paragraphs 12 through 19.

Description

Memory device comprising a near-memory processing unit and memory management method performed by the memory device The following discloses a memory device including proximity memory processing and a memory management technique performed by the memory device. In large-scale computing environments, high-speed DRAM is increasingly dominating infrastructure spending, and this trend will worsen without architectural changes. Deployed memory costs can be reduced by replacing a portion of existing DRAM with slower but lower-cost memory media and building a tiered memory system where both tiers support direct addressing and caching. The aforementioned background technology was possessed or acquired during the process of deriving the present disclosure and cannot be considered as prior art disclosed to the general public prior to the filing of the present disclosure. FIG. 1 is a drawing illustrating examples of memory systems according to various embodiments. FIG. 2 is a flowchart illustrating an example of a memory management method performed by a memory device according to various embodiments. FIG. 3 is a block diagram illustrating an example configuration of a memory device according to various embodiments. FIG. 4 is a diagram illustrating an example of an operation for a memory device to select a hot sub-block according to various embodiments. FIG. 5 is a diagram illustrating an example of an operation in which a hot sub-block moves from a second memory device to a first memory device in a memory system according to various embodiments. Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Accordingly, actual implementations are not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or substitutions included in the technical concept described by the embodiments. Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component. When it is stated that a component is "connected" to another component, it should be understood that it may be directly connected to or coupled with that other component, or that there may be other components in between. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, terms such as "comprising" or "having" are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification. Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the attached drawings, identical components are given the same reference numeral regardless of the drawing number, and redundant descriptions thereof will be omitted. FIG. 1 is a drawing illustrating examples of memory systems according to various embodiments. A memory system (100) according to one embodiment may include a host processor (110), a first memory device (120), a second memory device (130), and a bus (140). The memory system (100) may include a tiered memory system (100). A tiered memory system (100) may refer to a system that manages memory devices connected to the host processor (110) by dividing them into layers. In a tiered memory system, the memory device in the upper layer may be a memory device having a fast access speed and/or a small capacity, and the memory device in the lower layer may be a memory device having a slow access speed and/or a large capacity. According to one embodiment, the host processor (110) can perform major computation and/or control functions of the memory system (100). The host processor (110) may include at least one processor (111) and a memory controller. The processor (111) may, for example, include a CPU, a GPU, or an NPU, etc. The memory controller can control data transfer with a memory device (e.g., a first memory device (120), a second memory device (130)) connected to the host processor (110). According to one embodiment, the first memory device (120) may be a