KR-20260066422-A - SEMICONDUCTOR PACKAGE

KR20260066422AKR 20260066422 AKR20260066422 AKR 20260066422AKR-20260066422-A

Abstract

A semiconductor package may include: a first semiconductor chip; second semiconductor chips stacked vertically on the first semiconductor chip; a first bonding film structure interposed between the second semiconductor chips and comprising a first bonding pad structure; and a buried pattern comprising silicon oxide or a polymer, which contacts a portion of the sidewall of each of the second semiconductor chips, and one sidewall is aligned vertically with one sidewall of the first semiconductor chip. The first bonding film structure may include a first bonding film and a second bonding film that are stacked along the vertical direction and contact each other, and the first bonding pad structure may include first and second bonding pads that are respectively disposed within the first and second bonding films and contact each other. The first bonding film may contact the upper surface of a second semiconductor chip disposed relatively lower among the second semiconductor chips, and the second bonding film may contact the lower surface of a second semiconductor chip disposed relatively upper among the second semiconductor chips.

Inventors

장주희
이호진
김석호
임동찬

Assignees

삼성전자주식회사

Dates

Publication Date: 20260512
Application Date: 20241104

Claims (10)

First semiconductor chip; Second semiconductor chips stacked vertically on the first semiconductor chip; A first bonding film structure interposed between the second semiconductor chips and comprising a first bonding pad structure; and Each of the second semiconductor chips is in contact with at least a portion of the sidewalls, one sidewall is aligned in the vertical direction with one sidewall of the first semiconductor chip, and has an embedded pattern comprising silicon oxide or a polymer, The first bonding membrane structure comprises a first bonding membrane and a second bonding membrane that are stacked along the vertical direction and come into contact with each other. The first bonding pad structure comprises first and second bonding pads that are respectively disposed within the first and second bonding membranes and come into contact with each other. The first bonding film contacts the upper surface of a second semiconductor chip disposed in a relatively lower layer among the second semiconductor chips, and The second junction film is a semiconductor package that contacts the lower surface of a second semiconductor chip disposed relatively upper among the second semiconductor chips.
In claim 1, the polymer included in the embedded pattern comprises a semiconductor package comprising benzocyclobutene (BCB), polyimide (PI), or imide-phenol resin.
A semiconductor package according to claim 1, wherein the planar area of the first junction film is larger than the planar area of the second junction film.
In claim 1, the embedded pattern is a semiconductor package in contact with one sidewall of the second junction film.
In claim 1, the embedded pattern is a semiconductor package in contact with the upper surface of the edge portion of the first junction film.
In claim 1, each of the second semiconductor chips A substrate having first and second surfaces formed on opposite sides in the above vertical direction; A protective pattern structure disposed on the second surface of the substrate and in contact with the lower surface of the first bonding film structure; and A semiconductor package comprising a penetrating electrode structure penetrating the substrate and the protective pattern structure.
In claim 6, the semiconductor package in which the planar area of the protective pattern structure is larger than the planar area of the substrate.
In claim 6, the embedded pattern is a semiconductor package in contact with the lower surface of the edge portion of the protective pattern structure.
First semiconductor chip; A bonding film structure disposed on the first semiconductor chip and including a bonding pad structure; It is disposed on the above bonding membrane structure, and A substrate having first and second surfaces formed opposite each other in a vertical direction; An interlayer insulating film disposed below the first surface of the substrate and in contact with the upper surface of the bonding film structure; A protective pattern structure formed on the second surface of the substrate; and A second semiconductor chip comprising a through electrode structure that penetrates the substrate, the interlayer insulating film, and the protective pattern structure to contact the bonding pad structure; and A semiconductor package disposed on the above-mentioned bonding film structure and in contact with the sidewall of the substrate, the sidewall of the interlayer insulating film, and the lower surface of the above-mentioned protective pattern structure, and having an embedded pattern comprising silicon oxide or a polymer.
Buffer die; Middle core dies arranged along a vertical direction on the above buffer die; A first bonding membrane structure disposed between the buffer die and the middle core die disposed at the lowest layer among the middle core dies, and comprising a first bonding pad structure; A second bonding membrane structure disposed between the above middle core dies and comprising a second bonding pad structure; A third bonding membrane structure disposed on a middle core die disposed on the uppermost layer among the above middle core dies, and comprising a third bonding pad structure; A top core die disposed on the above-mentioned third bonding membrane structure; and A semiconductor package having a buried pattern comprising silicon oxide or a polymer, wherein one sidewall contacts a portion of the sidewalls of each of the above middle core dies, and one sidewall is aligned in the vertical direction with one sidewall of the buffer die.

Description

Semiconductor Package The present invention relates to a semiconductor package, and more specifically, to a multi-chip package comprising a plurality of stacked chips. A High Bandwidth Memory (HBM) package includes multiple memory chips stacked vertically on a logic chip, which can be bonded to each other through an adhesive layer. Since the bonding state between the memory chips must be good for the HBM package to have excellent performance, research on this is necessary. FIG. 1 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments. FIGS. 2 to 17 are plan and cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 18 to 20 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 21 to 26 are plan and cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 27 to 31 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIG. 32 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments. FIG. 33 is a cross-sectional view illustrating an electronic device according to exemplary embodiments. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Where materials, layers (films), regions, pads, electrodes, patterns, structures, or processes are referred to as "first," "second," and/or "third" in this specification, it is not intended to limit these components but merely to distinguish each material, layer (film), region, electrode, pad, pattern, structure, and process. Accordingly, "first," "second," and/or "third" may be used selectively or interchangeably for each material, layer (film), region, electrode, pad, pattern, structure, and process. In the following, among the horizontal directions parallel to the upper surface of each substrate or wafer, two directions that intersect each other are referred to as the first and second directions (D1, D2), respectively, and a vertical direction perpendicular to the upper surface of each substrate or wafer is referred to as the third direction (D3). In one embodiment, the first and second directions (D1, D2) may be orthogonal to each other. FIG. 1 is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments. Referring to FIG. 1, the semiconductor package may include a first semiconductor chip (100), a plurality of second semiconductor chips (200), and a third semiconductor chip (400) stacked sequentially along a third direction (D3). Additionally, the semiconductor package may further include first to third bonding film structures, first to third embedded patterns (305, 307, 407), a conductive pad (140), and a first conductive connection member (150). In exemplary embodiments, the semiconductor package may be a High Bandwidth Memory (HBM) package. In exemplary embodiments, the first semiconductor chip (100) may be a buffer die and may include a logic element such as a controller, for example, and each of the second and third semiconductor chips (200, 400) may be a core die and may include a volatile memory element such as a DRAM element, an SRAM element, for example, or a non-volatile memory element such as a flash memory element, an EEPROM element, for example. In this case, each of the second semiconductor chips (200) may be referred to as a middle core die and the third semiconductor chip (400) may be referred to as a top core die. Meanwhile, the first semiconductor chip (100) may be referred to as a logic chip or logic die, and each of the second and third semiconductor chips (200, 400) may be referred to as a memory chip or memory die. The first semiconductor chip (100) may include a first substrate (110) having first and second surfaces (112, 114) formed opposite each other in a third direction (D3), a first interlayer insulating film and a second interlayer insulating film (130) sequentially stacked along the third direction (D3) below the first surface (112) of the first substrate (110), a first protective pattern structure (160) formed on the second surface (114) of the first substrate (110), and a first penetrating electrode structure (120) extending in the third direction (D3) through the first substrate (110), the first interlayer insulating film, the second interlayer insulating film (130), and the first protective pattern structure (160). The first substrate (110) may include, for example, semiconductor materials such as silicon, germanium, silicon-germanium, etc., or group III-V compound semiconductors such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc. According to some embodiments, the first substrate (110) may be a silicon-on-insulato