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KR-20260066433-A - Electronic device including embedded MRAM device

KR20260066433AKR 20260066433 AKR20260066433 AKR 20260066433AKR-20260066433-A

Abstract

The electronic device comprises a plurality of wiring layers disposed on a substructure, an insulating structure disposed on the plurality of wiring layers, a Magnetic Random Access Memory (MRAM) device region including a plurality of memory cells disposed on the insulating structure, and a logic device region disposed adjacent to the MRAM device region. In the MRAM device region, each of the plurality of memory cells comprises a variable resistor structure, a lower electrode contact interposed between a first wiring layer selected among the plurality of wiring layers and the variable resistor structure, wherein the lower electrode contact has a lower inclined sidewall in contact with the insulating structure, an upper inclined sidewall that is closer to the variable resistor structure than the lower inclined sidewall and is spaced apart from the lower inclined sidewall and inclined in an inclined direction different from the inclined direction of the lower inclined sidewall, an insulating ring disposed on the insulating structure and filling a concave corner space defined by the upper inclined sidewall of the lower electrode contact and the edge portion of the bottom surface of the variable resistor structure, and contacts the sidewall of the variable resistor structure and the outer sidewall of the insulating ring, respectively, and the insulating ring between It includes an insulating liner spaced horizontally from the upper inclined side wall of the lower electrode contact.

Inventors

  • 정형종

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260512
Application Date
20241104

Claims (10)

  1. A plurality of wiring layers arranged on a substructure, and An insulating structure disposed on the plurality of wiring layers above, and A Magnetic Random Access Memory (MRAM) device region comprising a plurality of memory cells disposed on the insulating structure, and It includes a logic element region disposed adjacent to the above MRAM element region, and In the MRAM element region, each of the plurality of memory cells A variable resistor structure and, A lower electrode contact interposed between a first wiring layer selected from the plurality of wiring layers and a variable resistor structure, the lower electrode contact having a lower inclined sidewall in contact with the insulating structure, and an upper inclined sidewall that is more adjacent to the variable resistor structure than the lower inclined sidewall, is spaced apart from the lower inclined sidewall, and is inclined in an inclined direction different from the inclined direction of the lower inclined sidewall. An insulating ring disposed on the insulating structure and filling a concave corner space defined by the upper inclined sidewall of the lower electrode contact and the edge portion of the bottom surface of the variable resistor structure, and An electronic device comprising an insulating liner that is in contact with each of the sidewalls of the variable resistor structure and the outer sidewall of the insulating ring, and is spaced horizontally from the upper inclined sidewall of the lower electrode contact with the insulating ring in between.
  2. In paragraph 1, The above lower electrode contact is A first contact plug portion penetrating the above insulating structure in a vertical direction and having the above lower inclined side wall, and An electronic device comprising a second contact plug portion integrally connected to the first contact plug portion and having an upper inclined side wall, a bottom surface in contact with the upper surface of the insulating structure, and a top surface in contact with the center portion of the bottom surface of the variable resistor structure.
  3. In paragraph 2, The first contact plug portion has a shape in which the width in the horizontal direction increases as it approaches the variable resistor structure along the vertical direction from the first wiring layer. The electronic device having a shape in which the width in the horizontal direction decreases as it approaches the variable resistor structure along the vertical direction from the upper surface of the insulating structure.
  4. In paragraph 2, An electronic device having, in the above horizontal direction, a first contact plug portion having a first maximum width and a second contact plug portion having a second maximum width greater than the first maximum width.
  5. In paragraph 1, The above insulating ring is An inner side wall in contact with the upper inclined side wall of the lower electrode contact, and An electronic device having an upper surface that contacts the edge portion of the lower surface of the variable resistor structure.
  6. In paragraph 1, An electronic device in which the side wall of the variable resistor structure and the outer side wall of the insulating ring are on a straight line extending along a single plane.
  7. In paragraph 1, The above insulating ring is an electronic device having a shape in which the width in the horizontal direction gradually increases as it approaches the bottom surface of the variable resistor structure above the upper inclined side wall of the lower electrode contact.
  8. In paragraph 1, An electronic device in which the insulating ring and the insulating liner are made of different insulating materials.
  9. In paragraph 1, The above variable resistor structure lower electrode and, upper electrode and, It includes a first magnetization layer, a tunnel barrier layer, and a second magnetization layer sequentially stacked between the lower electrode and the upper electrode, An electronic device in which either of the first magnetization layer and the second magnetization layer comprises a fixed layer, and the other of the first magnetization layer and the second magnetization layer comprises a free layer.
  10. In Paragraph 9, The lower electrode contact is made of Ta, TaN, Co, TiN, Al, W, or a combination thereof, and The lower electrode included in the above variable resistor structure is an electronic device made of Ti, Ta, Ru, TiN, TaN, W, or a combination thereof.

Description

Electronic device including embedded MRAM device The technical concept of the present invention relates to an electronic device, and in particular to an electronic device comprising an embedded Magnetic Random Access Memory (MRAM) element. Recently, with the rapid proliferation of electronic devices such as smartphones, the development and adoption of System in Package (SiP) modules—which integrate multiple individual semiconductor chips into a single package to perform various functions in conjunction with said electronic devices—and wearable devices utilizing such modules are increasing. Consequently, there is a demand for technologies to mutually complement or enhance the functions of different products, and consequently, the development of convergence technologies is required in various fields. As electronic devices become faster and lower in power consumption, fast read/write operations and low operating voltage are required for memory devices embedded in these devices. MRAM devices are being researched as memory devices that meet these requirements. FIG. 1 is a plan view for illustrating an electronic device according to embodiments of the technical concept of the present invention. Figure 2 is a cross-sectional view along the line X1 - X1' of Figure 1. Figure 3 is an enlarged cross-sectional view of the part labeled "EX1" in Figure 2. Figure 4 is an enlarged cross-sectional view of the part labeled "EX2" in Figure 2. FIGS. 5a to 5t are cross-sectional views illustrated in the order of process to explain an exemplary method of manufacturing an electronic device according to the technical concept of the present invention. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1 is a plan view for explaining an electronic device (100) according to embodiments of the technical concept of the present invention. FIG. 2 is a cross-sectional view along the line X1-X1' of FIG. 1. FIG. 3 is an enlarged cross-sectional view of the portion marked "EX1" in FIG. 2. FIG. 4 is an enlarged cross-sectional view of the portion marked "EX2" in FIG. 2. An electronic device (100) according to the technical concept of the present invention will be explained with reference to FIG. 1 to FIG. 4. Referring to FIGS. 1 through 4, the electronic device (100) may include an MRAM element region (100A) and a logic element region (100B) disposed adjacent to the MRAM element region (100A). In this specification, the MRAM element region (100A) may be referred to as an embedded MRAM (eMRAM). The MRAM element region (100A) may include a cell region (CA) and a core/periphery region (CPA). As used in this specification, the term "core/periphery region" refers to a region including a core region surrounding the cell region (CA) and a peripheral circuit region surrounding the cell region (CA) and the core region. A plurality of magnetic tunnel junction (MTJ) structures may be disposed in the cell region (CA) of the MRAM element region (100A). As illustrated in FIG. 1, the logic element region (100B) may be arranged to surround the MRAM element region (100A) in a planar view, but the technical concept of the present invention is not limited thereto. The logic element region (100B) may include standard cells that perform desired logical functions, such as a counter or a buffer. The standard cells may include various types of logic cells that include a plurality of circuit elements, such as transistors or registers. The logic cells include, for example, AND, NAND, OR, NOR, XOR (exclusive OR), XNOR (exclusive NOR), INV (inverter), ADD (adder), BUF (buffer), DLY (delay), FIL (filter), and multiplexers (MXT/MXIT). OAI (OR/AND/INVERTER), AO (AND/OR), AOI (AND/OR/INVERTER), D flip-flop, reset flip-flop, master-slave flip-flop, latch, etc. can be configured. As illustrated in FIG. 2, the MRAM element region (100A) of the electronic device (100) may include a lower structure (102), a lower wiring structure (106) and a lower insulating layer (112) sequentially stacked on the lower structure (102), and a plurality of wiring layers (114) penetrating the lower insulating layer (112) in a vertical direction (Z direction). The substructure (102) may include a substrate composed of a semiconductor layer such as silicon (Si) or germanium (Ge), or a compound semiconductor layer such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. As used herein, the terms "SiGe," "SiC," "GaAs," "InAs," "InGaAs," and "InP" refer to materials composed of elements included in each term and are not chemical formulas representing stoichiometric relationships. The substructure (102) may further include a conductive region, for example, an impurity-doped well, or an impurity-doped structure. The substructure (102) may further include circuit patterns disposed on the substrate. In the cell re