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KR-20260066451-A - METHOD FOR CHECKING GATE DRIVER DATA AND APPARATUS THEREOF

KR20260066451AKR 20260066451 AKR20260066451 AKR 20260066451AKR-20260066451-A

Abstract

A method for verifying gate driver data according to one embodiment of the present disclosure comprises: a step of calculating duty information of a duty signal corresponding to a data value based on a clock signal of a high voltage section; a step of obtaining a normalized value by normalizing the duty information of the duty signal to a value of a certain number of bits; a step of calculating period information of a synchronization signal based on a clock signal of a low voltage section; and a step of compensating the duty information of the duty signal using the normalized value and the period information of the synchronization signal.

Inventors

  • 정보윤
  • 이수호
  • 조원희
  • 최윤호
  • 윤관

Assignees

  • 현대모비스 주식회사

Dates

Publication Date
20260512
Application Date
20241104

Claims (10)

  1. A step of calculating duty information of a duty signal corresponding to a data value based on a clock signal of a high-voltage section; A step of obtaining a normalized value by normalizing the duty information of the above duty signal into a value of a certain number of bits; Step of calculating period information of a synchronization signal based on a clock signal of a low-voltage section: and A step of compensating the duty information of the duty signal using the normalized value and the period information of the synchronization signal. A method for verifying gate driver data, including
  2. In paragraph 1, The step of obtaining the above normalized value is, A gate driver data verification method for obtaining the normalized value using the above-mentioned value of a fixed number of bits, the duty information of the duty signal, and the period information of the duty signal.
  3. In paragraph 1, The step of compensating for the duty information of the above duty signal is, A gate driver data verification method that compensates for the duty information of the duty signal using the normalized value, the value of a certain number of bits, and the period information of the synchronization signal.
  4. In paragraph 1, Step of obtaining the data value using the above compensated duty information A method for checking gate driver data, further including
  5. In paragraph 1, The step of calculating the duty information of the above duty signal is: A gate driver data verification method that calculates duty information of the duty signal and period information of the duty signal by counting the duty and period of the duty signal as a clock signal of the high voltage section.
  6. A first calculation unit that calculates duty information of a duty signal corresponding to a data value based on a clock signal of a high-voltage unit; A normalization unit that obtains a normalized value by normalizing the duty information of the above duty signal into a value of a certain number of bits; A second calculation unit that calculates period information of a synchronization signal based on a clock signal of a low-voltage unit: and A compensation unit that compensates the duty information of the duty signal using the normalized value and the period information of the synchronization signal. A gate driver data verification device including
  7. In paragraph 6, The above normalization unit is, A gate driver data verification device that obtains the normalized value using the above-mentioned value of a fixed number of bits, the duty information of the duty signal, and the period information of the duty signal.
  8. In paragraph 6, The above compensation unit is, A gate driver data verification device that compensates for the duty information of the duty signal using the normalized value, the value of a certain number of bits, and the period information of the synchronization signal.
  9. In paragraph 6, An acquisition unit that acquires the data value using the above-mentioned compensated duty information A gate driver data verification device further comprising
  10. In paragraph 6, The above-mentioned first output unit is, A gate driver data verification device that calculates duty information of the duty signal and period information of the duty signal by counting the duty and period of the duty signal as a clock signal of the high voltage section.

Description

Method for Checking Gate Driver Data and Apparatus Thereof The present disclosure relates to a technique for verifying gate driver data, and more specifically, to a data verification method and apparatus capable of improving data accuracy by reducing Pulse Width Modulation (PWM) deviation for each gate driver. Automotive gate driver ICs are core semiconductors for Integrated Charging Control Units (ICCUs) or Motor Control Units (MCUs). Conventional gate driver ICs are implemented by transmitting individual signals, transmitting and receiving information between the low-voltage section (or Primary Die) and the high-voltage section (or Secondary Die) via PWM signals. For signals requiring inter-die transmission—such as ON/OFF, fault, and temperature signals—existing gate driver ICs adopt an individual transmission method rather than a communication method to convey information. Figure 1 shows an example of a simulation result of propagation delay that occurs when data is transmitted through MOD/DEMOD. FIG. 2 shows an operation flowchart of a method for acquiring gate driver data according to one embodiment of the present disclosure. Figure 3 shows an example diagram to explain the operation performed in the low-voltage and high-voltage sections of a gate driver. Figure 4 shows an example diagram to explain the data acquisition process by 10-bit normalization. Figure 5 shows an example of the error rate that occurs when transmitting temperature information by 10-bit normalization. Figure 6 shows an example of the error rate that occurs when transmitting temperature information by 12-bit normalization. Figure 7 shows an example of the result of 10-bit normalization with varying conditions. FIG. 8 shows the configuration of a gate driver data acquisition device according to another embodiment of the present disclosure. FIG. 9 is a block diagram of a computing system for executing a gate driver data acquisition method according to one embodiment of the present disclosure. Hereinafter, embodiments of the present disclosure are described in detail with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present disclosure may be embodied in various different forms and is not limited to the embodiments described herein. In describing the embodiments of the present disclosure, if it is determined that a detailed description of known configurations or functions could obscure the essence of the present disclosure, such detailed description is omitted. Additionally, parts of the drawings unrelated to the description of the present disclosure have been omitted, and similar parts are denoted by similar reference numerals. In the present disclosure, when a component is described as being "connected," "combined," or "joined" with another component, this may include not only a direct connection but also an indirect connection in which another component exists in between. Furthermore, when a component is described as "comprising" or "having" another component, this means that, unless specifically stated otherwise, it does not exclude the other component but may include an additional component. In the present disclosure, terms such as first, second, etc. are used solely for the purpose of distinguishing one component from another component and do not limit the order or importance of the components unless specifically stated otherwise. Accordingly, within the scope of the present disclosure, a first component in one embodiment may be referred to as a second component in another embodiment, and likewise, a second component in one embodiment may be referred to as a first component in another embodiment. In the present disclosure, distinct components are intended merely to clearly explain their respective features and do not imply that the components are separate. That is, multiple components may be integrated to form a single hardware or software unit, or a single component may be distributed to form multiple hardware or software units. Accordingly, such integrated or distributed embodiments are included within the scope of the present disclosure, even if not otherwise mentioned. In the present disclosure, the components described in various embodiments do not necessarily mean essential components, and some may be optional components. Accordingly, embodiments consisting of a subset of the components described in one embodiment are also included within the scope of the present disclosure. Furthermore, embodiments including other components in addition to the components described in various embodiments are also included within the scope of the present disclosure. In the present disclosure, expressions of positional relationships used in this specification, such as upper, lower, left, right, etc., are provided for convenience of explanation, and when the drawings illustrated in this specification are viewed in reverse, the positional relationships described in the specification