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KR-20260066507-A - SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

KR20260066507AKR 20260066507 AKR20260066507 AKR 20260066507AKR-20260066507-A

Abstract

A semiconductor device comprises: a substrate including a first region and a second region; a gate structure located on the substrate and extending from the first region to the second region; a stack located on the second region on the substrate; first supports extending through the gate structure in the first region and arranged continuously in a first direction; and a second support in the second region extending in a second direction intersecting the first direction between the gate structure and the stack, wherein at least one of the first supports includes a first protrusion protruding toward the second region, and the second support may include a second protrusion protruding toward the first region.

Inventors

  • 김재호

Assignees

  • 에스케이하이닉스 주식회사

Dates

Publication Date
20260512
Application Date
20241104

Claims (20)

  1. A substrate including a first region and a second region; A gate structure located on the substrate and extending from the first region to the second region; A laminate located in the second region on the substrate; First supports extending through the gate structure in the first region and arranged continuously in a first direction; and In the second region above, a second support extending in a second direction intersecting the first direction between the gate structure and the laminate. Includes, At least one of the first supports includes a first protrusion protruding toward the second region, and The second support member includes a second protrusion protruding toward the first region. Semiconductor device.
  2. In Article 1, At least one of the first supports is, A first body portion extending through the above gate structure; and In the gate structure above, the first protrusion protruding from the first body portion Semiconductor device.
  3. In Article 1, The above second support is, A second body portion extending through the gap between the gate structure and the laminate; and In the gate structure above, the second protrusion protruding from the second body part Semiconductor device.
  4. In Article 1, Third supports extending through the gate structure in the first region and extending in the first direction; and Fourth supports extending through the gate structure in the second region and continuously arranged in the first direction A semiconductor device further comprising
  5. In Paragraph 4, At least one of the third supports comprises a third body portion extending through the gate structure and a third protrusion protruding from the third body portion toward the second region within the gate structure, At least one of the fourth supports comprises a fourth body portion extending through the gate structure and a fourth protrusion protruding from the fourth body portion toward the first region within the gate structure. is a semiconductor device.
  6. In Article 1, The above gate structure is A first part having a first height; and A second part having a second height smaller than the first height, positioned on the first part. Semiconductor device.
  7. In Article 6, A first sub-channel structure extending through the first portion; and Channel structures each including a second sub-channel structure that extends through the second portion and is connected to the first sub-channel structure. A semiconductor device further comprising
  8. In Article 7, At least one of the first protrusion or the second protrusion is located at a level corresponding to the first sub-channel structure. Semiconductor device.
  9. In Article 1, The above gate structure includes alternately stacked insulating films and conductive films, and Contact vias extending through the gate structure and respectively connected to the conductive films, and located in the first region and the second region A semiconductor device further comprising
  10. In Article 1, Peripheral circuits located on the above substrate; and A contact plug extending through the above laminate and electrically connected to the surrounding circuit, and located in the second region A semiconductor device further comprising
  11. A gate structure comprising a first portion and a second portion located on the first portion; A stack located at a level corresponding to the above gate structure; First supports extending through the gate structure and arranged continuously in a first direction; and A second support extending in a second direction intersecting the first direction between the gate structure and the laminate Includes, At least one of the first supports includes a first protrusion protruding toward the second support, and the second support includes a second protrusion protruding toward the first supports. At least one of the first protrusion or the second protrusion is located at a level corresponding to the first part. Semiconductor device.
  12. In Article 11, A substrate further comprising a first region and a second region, and The gate structure is located on the substrate and extends from the first region to the second region, and The above laminate is located in the second region on the substrate Semiconductor device.
  13. In Article 12, The first protrusion protrudes toward the second region, and The second protrusion is protruding toward the first region. Semiconductor device.
  14. In Article 12, The above gate structure includes alternately stacked insulating films and conductive films, and Contact vias extending through the gate structure and respectively connected to the conductive films, and located in the first region and the second region A semiconductor device further comprising
  15. In Article 12, Peripheral circuits located on the above substrate; and A contact plug extending through the above laminate and electrically connected to the surrounding circuit, and located in the second region A semiconductor device further comprising
  16. In Article 11, At least one of the first supports is, A first body portion extending through the above gate structure; and Each of the first protrusions protruding from the first body portion within the gate structure above is included Semiconductor device.
  17. In Article 11, The above second support is, A second body portion extending through the gap between the gate structure and the laminate; and In the first gate structure above, the second protrusion protruding from the second body portion Semiconductor device.
  18. In Article 11, Third supports extending through the gate structure in the first region and extending in the first direction; and Fourth supports extending through the gate structure in the second region and continuously arranged in the first direction A semiconductor device further comprising
  19. In Article 18, At least one of the third supports comprises a third body portion extending through the gate structure and a third protrusion protruding from the third body portion toward the fourth supports within the gate structure, At least one of the fourth supports comprises a fourth body portion extending through the gate structure and a fourth protrusion protruding from the fourth body portion toward the third supports within the gate structure. is a semiconductor device.
  20. In Article 11, The above first part has a first height, The second part has a second height smaller than the first height. Semiconductor device.

Description

Semiconductor Device and Method of Manufacturing Semiconductor Device The present invention relates to an electronic device and a method for manufacturing an electronic device, and more specifically, to a semiconductor device and a method for manufacturing a semiconductor device. The integration density of a semiconductor device is primarily determined by the area occupied by a unit memory cell. Recently, as the improvement of integration density in semiconductor devices that form memory cells as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices that stack memory cells on a substrate are being proposed. In addition, various structures and manufacturing methods are being developed to improve the operational reliability of such semiconductor devices. FIGS. 1a to 1d are drawings for explaining a semiconductor device according to an embodiment of the present invention. FIGS. 2a to 2d are drawings for explaining a semiconductor device according to an embodiment of the present invention. FIGS. 3a to 3e are drawings for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 4a to 4d, FIGS. 5a to 5d, FIGS. 6a to 6d, FIGS. 7a to 7d and FIGS. 8a to 8d are drawings for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings. FIGS. 1a to 1d are drawings for explaining a semiconductor device according to an embodiment of the present invention. FIG. 1a is a plan view, FIG. 1b is a cross-sectional view along A-A’ of FIG. 1a, FIG. 1c is a cross-sectional view along B-B’ of FIG. 1a, and FIG. 1d is a cross-sectional view along C-C’ of FIG. 1a. Referring to FIGS. 1a through 1d, the semiconductor device may include a substrate (100), a peripheral circuit (PC), a stack (110S), a gate structure (110G), channel structures (120), first supports (130) and a second support (140). The semiconductor device may further include third supports (150), fourth supports (160), contact vias (170), contact plugs (180), slit structures (190), an interlayer insulating film (IL), an interconnection structure (IC), an isolation film (ISO), a source structure (SS), a first insulating spacer (SP1) and a second insulating spacer (SP2). The substrate (100) may include a first region (R1) and a second region (R2). The first region (R1) and the second region (R2) may be adjacent in a first direction (I). The first region (R1) may be a region where memory cells are located. The second region (R2) may be a region where contact plugs (180) electrically connected to a peripheral circuit (PC) are located. Contact vias (170) connected to conductive films (110C) of a gate structure (110G) may be located in the first region (R1) and the second region (R2), respectively. A peripheral circuit (PC) may be located on a substrate (100). For example, the peripheral circuit (PC) may be located in a second region (R2). However, it is not limited thereto, and the peripheral circuit (PC) may be located in a first region (R1) and a second region (R2). The peripheral circuit (PC) may include a transistor (1) and a capacitor, etc. The transistor (1) may include junctions (1A, 1B), a gate electrode (1D), and a gate insulating film (1C). Here, the gate insulating film (1C) may be located between the gate electrode (1D) and the substrate (100). A device isolation film (ISO) may be located within the substrate (100), an active region may be defined by the device isolation film (ISO), and a transistor (1) may be located in the active region. An interconnection structure (IC) may be located on a peripheral circuit (PC). An interconnection structure (IC) may be located within an interlayer insulating film (IL). Here, the interlayer insulating film (IL) may be located on a substrate (100). The interconnection structure (IC) may include vias (ICA) and wirings (ICB). The interconnect structure (IC) can be connected to a peripheral circuit (PC). For example, at least one of the vias (ICA) can be connected to a transistor (1). At least one of the vias (ICA) can interconnect the wirings (ICB). The wirings (ICB) can interconnect the vias (ICA). The interconnect structure (IC) may include a conductive material such as tungsten. The interlayer insulating film (IL) may include an insulating material such as an oxide. The source structure (SS) may be located on the interlayer insulating film (IL). The source structure (SS) may be a single film or a multilayer film. The source structure (SS) may include a conductive material such as polysilicon. A gate structure (110G) may be positioned on a substrate (100). The gate structure (110G) may extend from a first region (R1) to a second region (R2). The gate structure (110G) may include first insulating films (110A) and conductive films (110C) t