KR-20260066686-A - System and method for maintaining CXL-based cache coherency via optical communication links

Abstract

The present invention relates to a system and method for maintaining cache consistency in a memory pool environment and a processor connected via an optical communication line using the CXL protocol. The system (10) of the present invention includes a coherence directory (400) that stores the shared state and RTT mapping of each data block, a consistency controller (500) that transmits an invalidation signal to a shared device upon a write request, and a speculative execution support unit (600) that prevents the interruption of operations of the processor (100) during a long invalidation round-trip delay of the optical communication line (200). The consistency controller (500) removes unnecessary optical communication traffic with a snoop filtering module (510), minimizes invalidation delay with a WDM-based invalidation-dedicated channel (220), allows preemptive writes with an optimistic completion signal issuer (520), and reduces packet overhead with an invalidation batch processing unit (530). The speculative execution support unit (600) isolates the speculative operation result into a temporary register file (630), performs a phased confirmation with a partial commit unit (640), and restores the state in case of invalidation failure with a checkpoint management unit (650). By doing so, processor stoppage caused by optical communication invalidation delays in AI inference and HPC workloads is eliminated.

Inventors

• 안범주

Assignees

• 안범주

Dates

Publication Date

20260512

Application Date

20260421

Claims (1)

1. In a system for maintaining data consistency in a CXL (Compute Express Link) environment where processors and memory pools are connected via optical communication lines, A coherence directory storing shared state and ownership information for each data block of the above memory pool; A consistency controller that, when a data modification request is received from the processor, transmits an invalidation signal to other devices holding a copy of the data by referring to the coherence directory; and To compensate for the transmission delay of the optical communication line, the above includes a speculative execution support unit that allows the processor to perform the next operation before a response to the invalidation signal is received. Optical communication-based CXL cache consistency maintenance system.

Description

System and method for maintaining CXL-based cache coherency via optical communication links System and method for maintaining CXL-based cache coherency via optical communication links The present invention relates to the field of semiconductor memory systems and high-speed interconnect technology, and more specifically, to a cache consistency maintenance system and method in a distributed computing environment in which a plurality of processors supporting the Compute Express Link (CXL) protocol and a memory pool are connected via an optical communication line, wherein a coherence directory-based invalidation protocol is applied, and processor stoppage caused by the long Round Trip Time (RTT) of the optical communication line is compensated for using a speculative execution technique. As training and inference workloads for artificial intelligence (AI) models surge in data centers, executing Large Language Models (LLMs) that process hundreds of billions of parameters requires memory resources on the scale of tens of terabytes, exceeding the memory capacity of a single server. To address this, Memory Disaggregation architectures, which integrate physically distributed memory modules into shared resources, are emerging as a core data center technology. The Compute Express Link (CXL) standard is an open interconnect standard led by Intel Corporation with participation from major tech companies such as Alibaba, Google, and Microsoft. It defines three subprotocols—CXL.io, CXL.cache, and CXL.mem—on top of the PCIe (PCI Express) physical layer and provides Cache-Coherent Memory Semantics. Starting with CXL 2.0, memory pooling via the CXL switch is supported, and with CXL 3.0, hardware-assisted memory sharing is standardized, making it possible for multiple host processors to share the same memory space coherently. However, current CXL standards are designed based on the PCIe 5.0/6.0 electrical signal-based physical layer, limiting transmission distances to only tens of centimeters to a few meters. To configure memory pools distributed across tens of meters to several kilometers within a data center, CXL connectivity must be extended via optical communication lines. Optical communication line-based CXL connectivity (hereinafter referred to as 'Optical Communication CXL') leverages the low-loss, high-bandwidth, and long-distance transmission characteristics of optical fibers to enable access to memory pools at distances inaccessible to electrical signal-based CXL. Lightelligence announced Photowave, a CXL over optical fiber solution, in 2023, and Samtec and MACOM have also commercialized PCIe/CXL extension solutions via optical fiber, respectively. Maintaining cache coherency in an optical communication CXL environment entails fundamentally different technical challenges compared to electrical signal-based CXL. In electrical signal-based CXL, cache coherence is maintained through the MESI (Modified, Exclusive, Shared, Invalid) state machine and Snoop mechanism of the CXL.cache protocol. For a processor to perform a write operation on shared data, it must send an invalidation signal to the caches of all other processors holding copies of that data, and the write operation can only be completed after receiving an acknowledgment of invalidation completion (ACK) from all other processors. In electrical signal-based CXL, this invalidation round-trip delay is at the level of tens of nanoseconds (ns), which is only tens of cycles relative to the clock cycles of modern processors, resulting in minimal performance degradation. However, in optical communication lines, the propagation speed of optical signals is approximately 2 × 10⁸ m/s, which is about two-thirds the speed of light in a vacuum. Consequently, the one-way delay per 100 meters of optical fiber reaches about 500 nanoseconds, and the round-trip delay reaches about 1 microsecond (μs). For a 1-kilometer section of optical fiber, the round-trip delay reaches about 10 microseconds. This is tens to hundreds of times longer than the invalidation round-trip delay of electrical signal-based CXL. In optical communication CXL environments where the invalidation round-trip delay reaches several microseconds to tens of microseconds, the processor stalls for thousands of clock cycles or more while waiting for an invalidation ACK to complete a write operation, causing severe performance degradation in AI inference and HPC workloads. This problem is a technical challenge unique to optical communication CXL that cannot be solved by simply applying existing electrical signal-based CXL coherence technology. Furthermore, while the Back Invalidation mechanism of CXL 3.0 standardized hardware coherence memory sharing, it was also designed based on short-range RTTs using electrical signals and does not provide an invalidation delay compensation mechanism specialized for the long RTTs of optical communication lines. As such, there is currently no known technical solution to minimize pro