KR-20260066687-A - Calibration method and apparatus for FPGA-based time-to-digital converter using time-bin sequence reconstruction

KR20260066687AKR 20260066687 AKR20260066687 AKR 20260066687AKR-20260066687-A

Abstract

The calibration method and apparatus for an FPGA-based time-to-digital converter according to the present invention solves the problem of missing code caused by the mixing of time bin sequences due to hardware wiring delays. A partial order, which is the physical precedence relationship between time bins, is derived from a data pattern obtained through a code density test, and after modeling this as a directed acyclic graph, phase alignment is performed to reconstruct a sequence that matches the actual physical arrangement. By utilizing Ansatsu and error libraries to reduce computational complexity and precisely correcting nonlinearity at the hardware level through FPGA resynthesis and lookup table updates, high-precision time measurement with picosecond resolution is enabled.

Inventors

박선우
박병권
김은성
윤지원

Assignees

에스디티 주식회사

Dates

Publication Date: 20260512
Application Date: 20260424

Claims (18)

As a method for correcting the time bin sequence of an FPGA-based time-to-digital converter (TDC), A code density test step in which an external signal is input to the time-to-digital converter by a delay line hardware unit included in a signal generator and an FPGA to generate a raw thermometer code from the delay line hardware unit and measure the detection frequency for each of a plurality of time bins; A step of deriving a partial order, which is the physical precedence relationship between time bins, by analyzing a pattern from the results of the code density test by a correction controller in which another time bin is deactivated when a specific time bin is activated; A step of generating a Directed Acyclic Graph (DAG) by the correction controller, wherein the derived plurality of partial sequences are edges and the time bins are nodes; A step of reconstructing a time bin sequence that matches the physical actual arrangement of the internal delay lines of the time-digital converter by phase-aligning the directed acyclic graph generated by the correction controller; and A step of physically modifying the lookup table information of a hardware encoder that converts the raw thermometer code into a valid time bin index based on the reconstructed time bin sequence by the correction controller; including Method for correcting time empty sequences.
In paragraph 1, The step of deriving the above partial order is, A step of detecting a missing code phenomenon in which a specific time bin A is activated in the perceived sequence but is not output during actual signal propagation; and Characterized by including the step of generating a directed edge by analyzing the relative arrival time difference between preceding and succeeding bins based on the missing bin, based on the fact that the cause of the above-mentioned missing code is a skip caused by a permutation mismatch between time bins. Method for correcting time empty sequences.
In paragraph 1, The step of deriving the above partial order is, A step of detecting an asymmetric activation pattern in which, among a plurality of time bins, when the first bin is activated, the second bin is always deactivated, but when the second bin is activated, the first bin remains active; and A step of determining a physical precedence relationship by interpreting the above asymmetric activation pattern as the first bin being electrically downstream of the second bin and masking the signal of the second bin, Method for correcting time empty sequences.
In paragraph 1, Characterized by further including a post-processing step that remaps the allocation order of time bins at the encoder level without modifying the physical logic of the hardware, based on the above-mentioned reconstructed time bin sequence. Method for correcting time empty sequences.
In paragraph 1, A step of setting an Ansatsu, which is a predefined expected permutation based on the uniform architectural characteristics of the FPGA, as a starting point before generating the above-mentioned directed acyclic graph; and a step of comparing the Ansatsu with the actual measured missing code pattern to select only specific units requiring correction among hundreds or more time bins and correct them independently; Characterized by further including, Method for correcting time empty sequences.
In paragraph 1, Characterized by grouping all time bins at regular intervals and correcting them independently to prevent interference between adjacent time bin blocks, Method for correcting time empty sequences.
In paragraph 6, The above constant interval is set in units of a specific number (n) of carry cells separated by a mutual interference distance or greater among a plurality of consecutive carry cells within the FPGA, and The above grouping is characterized by dividing and assigning the total carry cell index into n different exclusive groups based on the remainder of dividing the index by n, so that adjacent carry cell units are not operated within the same group. Method for correcting time empty sequences.
In paragraph 1, A step of inputting a pulse signal to be measured into the delay line to obtain a sampled digital code, and calculating the time length of the pulse signal to be measured corresponding to the digital code based on the reconstructed time bin sequence; including, Method for correcting time empty sequences.
As an FPGA-based time-to-digital converter system, A delay line hardware unit disposed inside the above FPGA, forming a signal propagation path through a plurality of serially connected carry cells and generating a raw thermometer code by tapping the propagation state of the signal in response to a sampling clock; and A correction controller that generates a directed acyclic graph through pattern analysis of data obtained from the above-mentioned delay line hardware unit, performs phase alignment to derive a reconstructed sequence, and updates the output mapping of the above-mentioned delay line hardware unit based on the reconstructed sequence; Characterized by including, and the correction controller being configured to physically change the lookup table information of a hardware encoder that converts the raw thermometer code into a valid time bin index according to the reconstructed sequence. Time bin sequence correction system.
In Paragraph 9, The above correction controller includes pattern analysis logic for detecting a missing code phenomenon in which a specific time bin A is not output during actual signal propagation, even though it is activated in the recognized order. Characterized by generating edges of the directed acyclic graph by analyzing the relative difference in arrival times between preceding and succeeding bins based on the aforementioned missing bin. Time bin sequence correction system.
In Paragraph 9, The correction controller is characterized by detecting an asymmetric activation pattern in which a second bin is deactivated when a first bin is activated, and interpreting that the first bin is physically positioned later than the second bin to mask the signal of the second bin, thereby determining the physical precedence relationship within the delay line hardware unit. Time bin sequence correction system.
In Paragraph 9, The hardware encoder includes a remapping circuit that rearranges each time bin index in correspondence with the reconstructed sequence, and the correction controller is characterized by dynamically controlling the data path of the remapping circuit without modifying the logic of the hardware. Time bin sequence correction system.
In Paragraph 9, The above correction controller includes a memory that stores an Ansatsu, which is a predefined expected permutation according to the uniform architectural characteristics of the FPGA, and Characterized by comparing the above Ansatsu with actual measurement data to select and activate only specific units requiring calibration among a plurality of time bin units. Time bin sequence correction system.
In Paragraph 9, The above correction controller includes a grouping control logic that groups the entire time bin into a specific number (n) set considering the interference distance between adjacent carry cell blocks, and the logic is characterized by separating each unit into different exclusive groups and correcting them in parallel according to the remainder (Modulo-n) value of n. Time bin sequence correction system.
A non-transient recording medium readable by a computing device, storing instructions that cause the computing device to perform a time bin sequence correction method when executed by the computing device, The above time bin sequence correction method is, A code density test step of controlling a delay line hardware unit included in a signal generator and an FPGA to input an external signal to the time-to-digital converter and generating a raw thermometer code from the delay line hardware unit to measure the detection frequency for each of a plurality of time bins; A step of analyzing the pattern in which another time bin is deactivated when a specific time bin is activated from the results of the above code density test to derive a partial order, which is the physical precedence relationship between the time bins; A step of generating a Directed Acyclic Graph (DAG) in which the plurality of derived partial sequences are edges and the time bins are nodes; A step of phase-aligning the generated directed acyclic graph to reconstruct a time bin sequence that matches the physical actual arrangement of the internal delay lines of the time-digital converter; including, A non-transient recording medium readable by a computing device.
In paragraph 15, The above time bin sequence correction method is characterized by further including, after the above reconstruction step, a step of physically changing the lookup table information of a hardware encoder that converts the raw thermometer code into a valid time bin index based on the above reconstruction time bin sequence. A non-transient recording medium readable by a computing device.
In paragraph 15, The above time bin sequence correction method is characterized by further including, after the reconstruction step, the step of inputting a pulse signal to be measured into the delay line to obtain a sampled digital code, and calculating the time length of the pulse signal to be measured corresponding to the digital code based on the reconstructed time bin sequence. A non-transient recording medium readable by a computing device.
In claim 15, the computing device is characterized as being a processing unit implemented inside the FPGA or an external computer device connected to communicate with the FPGA. A non-transient recording medium readable by a computing device.

Description

Calibration method and apparatus for FPGA-based time-to-digital converter using time-bin sequence reconstruction The present invention relates to a method for calibrating an FPGA-based time-to-digital converter, and more specifically, to a technique for solving missing code problems caused by a discrepancy between the design order and the actual placement of hardware by reconstructing the physical order of time bins inside a delay line using code density test data. The Time-to-Digital Converter (TDC) utilizes a spatial delay line (TDL) structure, in which logic elements are connected in series, to divide the time axis into fine intervals beyond the resolution of a high-frequency sampling clock. Precise time measurement is performed by sampling the state at each point as a signal propagates along the delay line using elements called time bins. However, when implementing ultra-high resolution at the picosecond (ps) level, delay variations and clock skew caused by complex routing paths within the FPGA act as significant variables. This results in inconsistent signal propagation speeds and causes a non-linear bin sequence problem where the intended index order in the design is mixed with the actual physical bin placement order. This inversion phenomenon causes ambiguous 0-1 transitions in the sampled thermometer code and results in a Missing Code phenomenon where certain time bins are not detected at all and are skipped. Consequently, the number of available valid bins is reduced, leading to a severe degradation of the time resolution and measurement accuracy of the TDC. FIGS. 1a and 1b are drawings illustrating a TDC architecture and a Z3 grouping concept according to an embodiment of the present invention. FIG. 2 is a diagram illustrating the principle of generating missing code due to a time bin sequence mismatch according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a partial order reconstruction algorithm for deriving the precedence relationship between time bins of a carry cell according to one embodiment of the present invention. Figure 4 is a diagram illustrating a partial order derived by the above algorithm in the form of a graph composed of nodes and edges. Figure 5 is a graph showing the change in the time bin recovery rate according to the number of times a partial order reconstruction algorithm according to an embodiment of the present invention is applied. Figure 6 is a figure illustrating a comparison of TDC nonlinearity and time bin width distribution characteristics before and after the application of partial order reconstruction technology according to one embodiment of the present invention. FIG. 7 is a configuration diagram illustrating a specific hardware architecture of a time bin sequence correction system according to one embodiment of the present invention. FIG. 8 is a configuration diagram illustrating the operation and implementation environment of a recording medium readable by a computing device according to an embodiment of the present invention. Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be implemented in various other forms. The terms used in this specification are intended to aid in understanding the embodiments and are not intended to limit the scope of the present invention. Furthermore, singular forms used below include plural forms unless the phrases clearly indicate otherwise. FIGS. 1a and 1b are drawings illustrating a TDC architecture and a Z3 grouping concept according to an embodiment of the present invention. Referring to FIG. 1a, the time-to-digital converter according to the present invention may be configured by utilizing a carry cell (100), which is a dedicated carry logic inside an FPGA, as a delay element. Specifically, the carry cell (100) may be a CARRY8 block (100 N-1 , 100 N , 100 N+1 , etc.) of the Xilinx UltraScale+ FPGA architecture, which may be defined as a minimum hardware unit for generating a plurality of time bins. A plurality of multiplexers (110) that form a delay line through which an input signal propagates may be connected in series inside the carry cell (100), and each output terminal of the multiplexer (110), called a tap, may be connected to the input terminal of a corresponding plurality of D-flip-flops (120). Looking at the sampling mechanism of the present invention, a pulse generator (200) can receive an external start (START, 201) signal and stop (STOP, 202) signal and generate an input pulse having a fixed duration. At this time, the 'external signal' mentioned in the claims of the present invention refers to the input signal (or input pulse) generated by the pulse generator (200), and the signal generating means including the pulse generator (200) may exist in various locations and forms depending on the system implementation environment. In one e