KR-20260066700-A - SEMICONDUCTOR DEVICE AND IMAGING DEVICE

Abstract

The present invention provides a semiconductor device that is fine and has low power consumption. A method for manufacturing a wiring layer, wherein a second insulator is formed on a first insulator, a third insulator is formed on the second insulator, an opening is formed in the third insulator to reach the second insulator, a first conductor is formed on the third insulator and in the opening, and a second conductor is formed on the first conductor, and then the second conductor and the first conductor located above the upper surface of the third insulator are removed by polishing, and the end of the first conductor is equal to or lower than the height of the end of the opening at the end of the opening, and the height of the upper surface of the second conductor is equal to or lower than the height of the end of the first conductor.

Inventors

• 오카자키 유타카
• 모리와카 토모아키
• 사사가와 신야
• 오츠키 다카시

Assignees

• 가부시키가이샤 한도오따이 에네루기 켄큐쇼

Dates

Publication Date

20260512

Application Date

20260506

Priority Date

20141001

Claims (2)

1. As a semiconductor device, Having a first insulating film to a third insulating film and a first conductor to a second conductor, Having the second insulating film on the first insulating film, The first conductor and the second conductor are provided in a contact hole provided in the second insulating film, and Having the second conductor on the first conductor, Having the third insulating film on the second insulating film and the second conductor, The first insulating film has a region in contact with the bottom surface of the first conductor, and The second insulating film has a region in contact with the upper surface of the first insulating film and a region in contact with the side surface of the first conductor, and The second conductor has a region in contact with the upper surface of the first conductor and a region in contact with the side surface of the first conductor, A semiconductor device having the third insulating film having a region in contact with the upper surface of the second insulating film, a region in contact with the side surface of the first conductor, and a region in contact with the upper surface of the second conductor.
2. As an imaging device, It has a pixel section and a first peripheral circuit to a fourth peripheral circuit, An imaging device in which the first to fourth peripheral circuits are each connected to a pixel provided in the pixel portion.

Description

Semiconductor Device and Imaging Device The present invention relates to an article, a method, or a method of manufacturing. Alternatively, the present invention relates to a process, a machine, a product, or a composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a capacitor, an imaging device, a memory device, a method of operating the same, or a method of manufacturing the same. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, or a light-emitting device having an oxide semiconductor. Furthermore, in this specification and others, the term "semiconductor device" refers to any device capable of functioning by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices may include semiconductor devices. As silicon used for transistor semiconductors, amorphous silicon and polycrystalline silicon are distinguished and used depending on the application. For example, for transistors used in large display devices, it is preferable to use amorphous silicon, for which film deposition technology on large-area substrates is established. On the other hand, for transistors used in high-performance display devices where the driving circuit and pixel section are formed on the same substrate, it is preferable to use polycrystalline silicon, which enables the fabrication of transistors with high field-effect mobility. Methods for forming polycrystalline silicon include high-temperature heat treatment of amorphous silicon or laser irradiation. In recent years, the development of transistors using oxide semiconductors (typically In-Ga-Zn oxide) has been actively underway. Transistors using oxide semiconductors possess characteristics different from those using amorphous silicon and polycrystalline silicon. For example, it is known that display devices utilizing oxide semiconductor transistors have low power consumption. In addition, it is known that transistors using oxide semiconductors have very low leakage current in the off state. For example, low-power consumption CPUs utilizing the characteristic of low leakage current of transistors using oxide semiconductors have been disclosed (see Patent Document 1). In order to reduce power consumption through power gating, it is desirable for a transistor using an oxide semiconductor to have a normally off electrical characteristic. As one method of controlling the threshold voltage of a transistor using an oxide semiconductor to have a normally off electrical characteristic, a floating gate is placed in a region overlapping with the oxide semiconductor, and a negative fixed charge is injected into the floating gate. This method is disclosed (see Patent Document 2). Since oxide semiconductors can be formed by methods such as sputtering, they can be used in transistors for large display devices. Furthermore, because transistors using oxide semiconductors possess high field-effect mobility, it is possible to realize high-performance display devices in which the driving circuit and pixel section are formed on the same substrate. Additionally, since parts of the production facilities used for transistors made of amorphous silicon or polycrystalline silicon can be modified and utilized, there is the advantage of reducing equipment investment. The history of oxide semiconductors is long, and the synthesis of crystalline In-Ga-Zn oxide was reported in 1985 (see Non-Patent Literature 1). Additionally, in 1995, it was reported that In-Ga-Zn oxide has a homologous structure and its compositional formula is represented as InGaO3 (ZnO) m (where m is a natural number) (see Non-Patent Literature 2). In addition, a transistor using an oxide semiconductor was invented in 1995, and its electrical characteristics are disclosed (see Patent Document 3). In addition, a transistor using a crystalline oxide semiconductor was reported in 2014 (see Non-patent Literature 3 and Non-patent Literature 4). Here, a transistor using CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) was reported, which is capable of mass production and has excellent electrical characteristics and reliability. As integrated circuits become miniaturized, the wiring layer becomes lower in resistance and more multilayered, making the flattening of the wiring layer an essential requirement. To solve this problem, a damascene process that embeds the wiring layer within an interlayer insulating film is widely used (see Non-Patent Literature 5). FIG. 1 is a cross-sectional view of a wiring layer according to one embodiment of the present invention. FIG. 2 is a drawing for explaining a method for manufacturing a wiring layer according to one embodiment of the present invention. FIG. 3 is a top view and a cross-sectional view of a transistor according to one embo