KR-20260066734-A - Power management based on frame slicing

Abstract

Systems, devices, and methods for implementing efficient power optimization in a computing system are disclosed. A system management unit configured to track computing activity of a computing device while processing each of a plurality of frames. The computing activity is tracked for at least a given period comprising a plurality of time slices. Based at least partially on the tracked computing activity, the system management unit further correlates a time slice associated with a given frame with a time slice associated with one or more previously processed frames from the plurality of frames. Based at least partially on the correlation, the system management unit predicts a clock frequency for rendering a given frame and renders the given frame using the predicted clock frequency.

Inventors

• 제인, 아쉬시
• 모기미, 아라쉬

Assignees

• 어드밴스드 마이크로 디바이시즈, 인코포레이티드
• 에이티아이 테크놀로지스 유엘씨

Dates

Publication Date

20260512

Application Date

20240918

Priority Date

20230929

Claims (20)

1. As a system, It includes a system management circuit, and the system management circuit comprises, Tracking computing activity of a computing device while processing two or more frames among multiple frames - each frame includes multiple time slices -; and A system configured to cause a clock generation circuit to generate a clock signal having a predicted clock frequency—the predicted clock frequency being at least partially based on the correlation between computing activity during a time slice of a first frame and computing activity during a time slice of a second frame.
2. A system according to claim 1, wherein the system management circuit is further configured to store data corresponding to the tracked computing activity for each time slice of the plurality of time slices for the plurality of frames.
3. In claim 1, the clock signal is used to render frame data, in a system.
4. A system according to claim 1, wherein the system management circuit is further configured to recalibrate the activity period of a given frame in response to a recalibration condition.
5. In paragraph 4, the recalibration condition comprises one or more of the following: a change in the frame length of the given frame, one or more unscheduled changes in the clock frequency or supplied power for the system, and one or more of tracked computing activity data that does not meet the given criteria.
6. A system according to claim 1, wherein the computing activity is stored as activity data, and the activity data is updated in response to a change in at least one characteristic associated with at least one frame among the plurality of frames.
7. A system according to claim 1, wherein the plurality of time slices are defined at least partially based on the processing time of each frame.
8. As a method, A step of tracking computing activity of a computing device while processing two or more frames among a plurality of frames - each frame includes a plurality of time slices -; and A method comprising the step of causing a clock generation circuit to generate a clock signal having a predicted clock frequency, wherein the predicted clock frequency is at least partially based on the correlation between computing activity during a time slice of a first frame and computing activity during a time slice of a second frame.
9. A method according to claim 8, further comprising the step of storing data corresponding to the tracked computing activity for each time slice of the plurality of time slices for the plurality of frames.
10. A method according to claim 8, further comprising the step of rendering frame data using the predicted clock frequency.
11. A method according to claim 8, further comprising the step of recalibrating the activity period of a given frame in response to the recalibration condition.
12. In claim 11, the recalibration condition comprises one or more of a change in the frame length of the given frame, one or more unscheduled changes in clock frequency or power, and one or more of tracked computing activity data that does not meet a given criterion.
13. In claim 8, the method wherein the computing activity is tracked in response to a change in at least one characteristic associated with at least one frame among the plurality of frames.
14. A method according to claim 8, wherein the plurality of time slices are defined at least partially based on the processing time of each frame.
15. As a computing system, A computing device configured to process frames; and It includes a system management circuit, and the system management circuit comprises, Tracking the computing activity of the computing device while processing each frame of a plurality of frames - said computing activity is tracked during a given time period including at least a plurality of time slices -; Based at least partially on the above-mentioned tracked computing activity, a time slice associated with a given frame is correlated with a time slice associated with at least one previously processed frame from a plurality of frames; Predicting the clock frequency associated with the rendering of the given frame based at least partially on the above correlation; and A computing system configured to render the given frame using the predicted clock frequency.
16. A computing system according to claim 15, wherein the system management circuit is further configured to store data resulting from the tracked computing activity for each time slice of the plurality of time slices for the plurality of frames.
17. In paragraph 15, the time slice associated with the given frame is a computing system correlated with the time slice associated with at least one previously processed frame, based on a comparison of the computing activity of the given frame and the computing activity tracked during the time slice associated with at least one previously processed frame.
18. In item 15, the above-mentioned system management circuit unit is, In response to a recalibration condition, recalibrate one or more time slices of the given frame; and A computing system further configured to modify one or more time slices of the given frame based on the above recalibration.
19. In item 15, the above-mentioned system management circuit is, In response to the identification of a recalibration condition, one or more time slices of the given frame are recalibrated; and A computing system further configured to modify one or more time slices of the given frame based on the above recalibration.
20. A computing system according to claim 19, wherein the recalibration condition comprises one or more of a change in the frame length of the given frame, one or more unscheduled changes in the clock frequency or supplied power for the system, and one or more tracked computing activity data that does not meet a given criterion.

Description

Power management based on frame slicing Description of related technology During the design of a computer or other processor-based system, many design factors must be considered. A successful design requires various trade-offs between power consumption, performance, and thermal output. For example, designing a computer system focused on high performance allows for greater power consumption. Conversely, the design of a portable computer system, sometimes powered by a battery, may emphasize reducing power consumption at the expense of some performance. Regardless of specific design goals, a computing system typically has a given amount of power available to it during operation. This power must be allocated among the various components within the system—some allocated to the central processing unit, others to the memory subsystem, and some to the graphics processing unit, and so on. The way power is allocated among system components can also change during operation. Processing systems typically employ various management techniques to manage operational system parameters, such as clock frequency and system power, to ensure the overall system operates effectively. For example, mechanisms like dynamic voltage and frequency scaling can help mitigate power management issues by adjusting power consumption in response to workload demands. Additionally, cooling systems assist in dissipating excess heat, enabling performance to be maintained while preserving system stability. Therefore, careful consideration of power management strategies is essential to guarantee optimal performance and lifespan in GPU processing environments. However, current management schemes for operational parameters are typically based on average behavior. For example, when frames are being rendered, the processing system calculates an appropriate power management scheme based on the average power dissipated over the last few rendered frames or graphics engine activity. This results in a conservative frequency selection that consumes unnecessary power, or alternatively, an average frequency selection that degrades the performance of certain phases of the frame. From the above perspective, an improved system and method for efficient system management for frame rendering are required. The advantages of the methods and mechanisms described in this specification can be better understood by referring to the following description together with the accompanying drawings. Figure 1 is a block diagram of one implementation example of a computing system. Figure 2 is a block diagram of another implementation example of a computing system. Figure 3 is a block diagram of one implementation example of a system management circuit section. FIG. 4 is a block diagram illustrating the tracking of computing activities during frame processing over one or more activity periods. FIG. 5 illustrates a method for tracking computing activity to predict one or more parameters of a task scheduled to be executed. In the following description, numerous specific details are provided to provide a complete understanding of the methods and mechanisms presented herein. However, those skilled in the art should recognize that various embodiments may be practiced without these specific details. In some cases, known structures, components, signals, computer program instructions, and techniques are not illustrated in detail to avoid obscuring the approaches described herein. For the sake of simplicity and clarity of example, it will be understood that the elements depicted in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated compared to others. Systems, devices, and methods for efficient power management in processing systems are disclosed. A system management circuit tracks the computing activity of a computing device while processing each frame of a plurality of frames. In various embodiments, the number of frames is fixed, programmable, and/or dynamically identified. The computing activity is tracked for at least a given period of time, which includes a plurality of frames, each frame being divided into a plurality of time slices. Based at least partially on the tracked computing activity, the system management circuit correlates the time slices during the processing of subsequent frames with the time slices during the processing of at least one previously processed frame among the plurality of frames, and predicts clock frequencies for rendering the frames. Subsequent frames are rendered using the predicted clock frequencies for each time slice during the frame. Now, referring to FIG. 1, a block diagram of one embodiment of a computing system (100) is shown. In this embodiment, the illustrated computing system (100) includes a system-on-chip (SoC) (105) coupled to memory (160). However, embodiments in which one or more of the illustrated components of the SoC (105) are not integrated on a single chip are possible and con