KR-20260066737-A - Via filling method

Abstract

A method for processing a substrate comprises the step of exposing the substrate to a boron-containing precursor to be adsorbed onto the substrate, wherein the substrate comprises a dielectric layer formed on a conductive layer, and the conductive layer is exposed at the bottom of a recess formed within the dielectric layer. The method comprises the step of exposing the adsorbed boron-containing precursor to a plasma, and the step of filling the recess with a conductive filler material in an upward manner by a vapor deposition process, wherein the vertical deposition rate of the conductive filler material is greater than the lateral deposition rate of the conductive filler material.

Inventors

• 요네자와 료타
• 유 카이-훙
• 트리케트 잉
• 스즈키 히데나오

Assignees

• 도쿄엘렉트론가부시키가이샤

Dates

Publication Date

20260512

Application Date

20240710

Priority Date

20230921

Claims (20)

1. As a method for processing a substrate, The above method is, A step of exposing the substrate to a boron-containing precursor for adsorption on the substrate, wherein the substrate comprises a dielectric layer formed on a conductive layer, and the conductive layer is exposed at the bottom of a recess formed within the dielectric layer; A step of exposing the adsorbed boron-containing precursor to plasma; and A step comprising filling the recess with a conductive filler material in a bottom-up manner by a vapor deposition process, wherein the vertical deposition rate of the conductive filler material is greater than the lateral deposition rate of the conductive filler material. Method for processing substrates.
2. In paragraph 1, The above boron-containing precursor comprises a boron halide or a boran, in a method.
3. In paragraph 1, The above boron -containing precursor comprises B₂H₆ , BF₃ , BCl₃ , or BBr₃ , in a method.
4. In paragraph 1, A method in which the conductive layer comprises ruthenium (Ru), tungsten (W), or titanium (Ti).
5. In paragraph 1, The above plasma comprises argon and hydrogen, method.
6. In paragraph 1, The above dielectric layer comprises silicon oxide, and The step of exposing to the plasma induces boron doping in the silicon oxide, a method.
7. In paragraph 1, A method in which the conductive filling material comprises ruthenium (Ru), tungsten (W), or molybdenum (Mo).
8. In paragraph 1, The step of exposing to the plasma above is a method for removing boron from the conductive layer.
9. As a method for processing a substrate, The above method is, A step of exposing the substrate to BCl3 for adsorption on the surface of the substrate, wherein the surface comprises a dielectric layer and a conductive layer; A step of exposing the adsorbed BCl3 to a plasma containing argon and hydrogen, wherein the step of exposing to the plasma comprises incorporating boron into the dielectric layer; and A step of depositing a metal on the above surface, wherein the deposition rate of the metal is greater on the conductive layer than on the dielectric layer, comprising the step of Method for processing substrates.
10. In Paragraph 9, A method comprising, prior to the deposition step, a step of repeating the step of exposing to BCl3 and the step of exposing to plasma.
11. In Paragraph 9, The above substrate includes a recess, A method in which the conductive layer is exposed at the bottom of the recess, and the dielectric layer comprises the sidewall of the recess.
12. In Paragraph 9, A method in which the step of exposing to BCl3 is performed in the absence of plasma.
13. In Paragraph 9, A method in which the metal comprises ruthenium (Ru), tungsten (W), or molybdenum (Mo).
14. In Paragraph 9, A method in which the conductive layer comprises titanium nitride or tantalum nitride.
15. A method for forming a metal interconnect for a semiconductor device, The above method is, A step of exposing a substrate containing said via to a boron-containing precursor for adsorption on the sidewall of the via, wherein said via has a critical dimension of 20 nm or less and a conductive material is exposed at the bottom of said via; A step of exposing the substrate to plasma to induce boron doping into the sidewall; and A step of filling the via with ruthenium (Ru) by a vapor deposition process, wherein the Ru is preferentially deposited from the bottom of the via rather than from the sidewall, comprising Method for forming a metal interconnect for a semiconductor device.
16. In paragraph 15, A method in which the above vias have an aspect ratio of 5:1 to 100:1.
17. In paragraph 15, A method in which the above via is filled with Ru without voids.
18. In paragraph 15, A method in which the boron-containing precursor comprises BCl3 , and the plasma comprises argon and hydrogen.
19. In paragraph 15, The above conductive material comprises titanium nitride, a method.
20. In paragraph 15, The above sidewall comprises an oxide, method.

Description

Via filling method Cross-reference regarding related patents and applications This application claims priority and benefit to the filing date of U.S. Regular Patent Application No. 18/471,823, filed September 21, 2023, the entirety of which is incorporated herein by reference. The present invention generally relates to a method for processing a substrate, and in a specific embodiment, to via filling. Generally, semiconductor devices such as integrated circuits (ICs) are manufactured by sequentially depositing and patterning layers of dielectric materials, conductive materials, and semiconductor materials on a substrate to form a network of electronic components and interconnect elements (e.g., transistors, resistors, capacitors, metal lines, contacts, and vias) integrated in a monolithic structure. A process flow commonly used to form the component structures of a semiconductor device includes the steps of depositing and removing various materials while a pattern of multiple materials can be exposed within the surface of a working substrate. The minimum dimensions of features within patterned layers are periodically reduced, nearly doubling component density at each successive technology node and thereby reducing the cost per feature. With innovations in patterning, such as immersion deep ultraviolet (i-DUV) lithography, multi-patterning, and 13.5 nm wavelength extreme ultraviolet (EUV) optical systems, some critical dimensions have been reduced to near 10 nanometers. As miniaturization progresses further, new problems are emerging in copper (Cu) wiring. Specifically, the wiring width used within the device has become much smaller than the mean free path of electrons within the Cu material, causing an increase in resistance values due to scattering. Therefore, new wiring materials for metal interconnects with excellent material properties, and their manufacturing technologies, may be desirable at increasingly smaller scales. A method for processing a substrate comprises the step of exposing the substrate to a boron-containing precursor to be adsorbed onto the substrate, wherein the substrate comprises a dielectric layer formed on a conductive layer, and the conductive layer is exposed at the bottom of a recess formed within the dielectric layer. The method comprises the step of exposing the adsorbed boron-containing precursor to a plasma, and the step of filling the recess with a conductive filler material in an upward manner by a vapor deposition process, wherein the vertical deposition rate of the conductive filler material is greater than the lateral deposition rate of the conductive filler material. A method for treating a substrate comprises the step of exposing the substrate to BCl3 for adsorption on the surface of the substrate, wherein the surface comprises a dielectric layer and a conductive layer. The method comprises the step of exposing the adsorbed BCl3 to a plasma comprising argon and hydrogen, wherein the step of exposing to the plasma incorporates boron into the dielectric layer. The method comprises the step of depositing a metal on the surface, wherein the deposition rate of the metal is greater on the conductive layer than on the dielectric layer. A method for forming a metal interconnect for a semiconductor device comprises the step of exposing a substrate containing a via to a boron-containing precursor to be adsorbed on the sidewall of the via, wherein the via has a critical dimension of 20 nm or less and a conductive material is exposed at the bottom of the via. The method comprises the step of exposing the substrate to a plasma to induce boron doping into the sidewall, and the step of filling the via with ruthenium (Ru) by a vapor deposition process, wherein Ru is preferentially deposited from the bottom of the via rather than from the sidewall. Now, for a more complete understanding of the present invention and its advantages, refer to the following description in conjunction with the accompanying drawings, and as the accompanying drawings: FIGS. 1a to 1f illustrate cross-sectional views of an exemplary substrate during an exemplary semiconductor manufacturing process including via filling at various stages according to various embodiments, wherein FIG. 1a illustrates an inset substrate including a recess in a dielectric layer, FIG. 1b illustrates a substrate after a boron exposure step, FIG. 1c illustrates a substrate after a plasma exposure step, FIG. 1d illustrates a substrate during a metal deposition step, FIG. 1e illustrates a substrate after the completion of the metal deposition step, and FIG. 1f illustrates a substrate after etch back and planarization; FIG. 2 shows a scanning electron microscope (SEM) cross-sectional image of an exemplary substrate after ruthenium (Ru) deposition having a boron exposure step; FIG. 3 shows a scanning electron microscope (SEM) cross-sectional image of an exemplary substrate after ruthenium (Ru) deposition without a boron exposure step; FIG.