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KR-20260066743-A - Manufacture of silicon through-vias

KR20260066743AKR 20260066743 AKR20260066743 AKR 20260066743AKR-20260066743-A

Abstract

A through-silicon via (TSV) and a method for manufacturing the same are disclosed. An exemplary TSV includes a core extending through a substrate along an axis. The core comprises a conductive material. The TSV also includes an outer layer positioned around the axis. The outer layer surrounds the core at least partially. The outer layer comprises a superconducting material. The TSV further includes an insulating layer that electrically insulates the core and the outer layer from each other.

Inventors

  • 밀러, 로버트
  • 데라크샨데, 자베르
  • 헤르, 안나

Assignees

  • 아이엠이씨 브이제트더블유

Dates

Publication Date
20260512
Application Date
20240911
Priority Date
20230915

Claims (20)

  1. As a through-silicon via (TSV), the through-silicon via is, Core - The core extends through the substrate along an axis, and the core comprises a conductive material; Outer layer - said outer layer is positioned around said axis and at least partially surrounds said core, said outer layer comprises a superconducting material; and A silicon through-via comprising: an insulating layer - said insulating layer electrically insulating the core and the outer layer from each other.
  2. In paragraph 1, A silicon through-via in which the core comprises at least one of Cu, Ni, Co, or Al.
  3. In paragraph 1 or 2, A silicon through-via, wherein the core is configured to operate at cryogenic temperatures and has a thermal conductivity of at least 200 W/m.
  4. In any one of paragraphs 1 through 3, A silicon through-via in which the outer layer comprises at least one of NbTiN, NbN, Nb₃Al , Nb, Ti, Al, Ta, or a combination of these materials.
  5. In any one of paragraphs 1 through 4, A silicon through-via in which the critical temperature of the outer layer is greater than 5K.
  6. In any one of paragraphs 1 through 5, A silicon through-via having an outer layer thickness of 10 to 100 nm.
  7. In any one of paragraphs 1 through 6, A silicon through-via having an insulating layer with a thickness of 30 to 50 nm.
  8. In any one of paragraphs 1 through 7, A silicon through-via in which the insulating layer comprises at least one of SiO2 or SiN.
  9. In any one of paragraphs 1 through 8, A silicon through-via wherein the insulating layer comprises a SiO2 film deposited using tetraethyl orthosilicate (TEOS) as a precursor.
  10. In any one of paragraphs 1 through 9, A silicon through-via, wherein the substrate comprises an interposer, and the interposer comprises silicon.
  11. In any one of paragraphs 1 through 10, A silicon through-via further comprising a capping layer forming the surface of the outer layer, wherein the capping layer comprises SiN or TaN.
  12. In any one of paragraphs 1 through 11, The above silicone through-via further includes an upper contact portion, and the upper contact portion is, Indium bumps electrically connected to the above outer layer; and A silicon through-via comprising a copper bump electrically connected to the core.
  13. A method for forming a through-silicon via (TSV), wherein the method comprises: Step of etching a cavity within a substrate; A step of forming a first insulating layer along the side wall of the cavity; A step of forming an outer layer on a first insulating layer within the cavity, wherein the outer layer comprises a superconducting material; A step of forming a second insulating layer on the outer layer within the cavity; A step of forming a seed layer on a second insulating layer within the cavity; and A method comprising the step of forming a core on a seed layer within the cavity, wherein the core comprises a conductive material.
  14. In Paragraph 13, After forming a core, a step of planarizing a first surface of a substrate through a chemical mechanical polishing (CMP) process; A step of patterning a first surface of a substrate; A step of forming a plurality of superconducting wires on a first surface of a substrate based on the above patterning; A step of thinning the second surface of the above substrate to a desired substrate thickness; A step of patterning a second surface of a substrate; and A method further comprising the step of forming a plurality of superconducting wires on a second surface of a substrate based on the patterning above.
  15. In paragraph 13 or 14, A method in which the above cavity has a depth-to-width aspect ratio of at least 10:1.
  16. In any one of paragraphs 13 through 15, A method comprising the step of etching the cavity described above, which includes using a Bosch etch process to obtain substantially vertical sidewalls.
  17. In any one of paragraphs 13 through 16, A method comprising forming the first insulating layer or forming the second insulating layer, wherein the method comprises a tetraethyl orthosilicate (TEOS)/ O3 process or a plasma enhanced atomic layer deposition (PEALD) process.
  18. In any one of paragraphs 13 through 17, A method further comprising the step of forming a capping layer on the superconducting material, wherein the capping layer comprises SiN or TaN.
  19. In any one of paragraphs 13 through 18, A method comprising the step of forming the seed layer, wherein the diffusion barrier layer comprises forming a diffusion barrier layer, wherein the diffusion barrier layer comprises at least one of Ta deposited by physical vapor deposition (PVD), TiN deposited by atomic layer deposition (ALD), or tungsten nitride (WN) deposited by ALD.
  20. In any one of paragraphs 13 through 19, A step of forming an indium bump along a first surface of the substrate so that the indium bump is electrically connected to the outer layer; and A method further comprising the step of forming a copper bump along a first surface of the substrate so that the copper bump is electrically connected to the core.

Description

Manufacture of silicon through-vias The present invention relates to the field of superconducting silicon through-silicon vias (TSVs). More specifically, it relates to a manufacturing process for forming a TSV having a core made of a conductive material and an outer layer made of a superconducting material, wherein the conductive layers are separated from each other by an oxide layer. Cryogenic technology is currently being considered as a potential solution for large-scale computational applications with high energy efficiency. Cryogenic systems can provide extremely high packaging densities on and between multiple substrates thanks to their operating temperatures. The three-dimensional integration of cryogenic-compatible circuits is considered a key potential factor for scaling up these systems. However, for three-dimensional integrated circuits with silicon interposers, there is no well-established packaging process that includes both superconducting metallization and general conductive metallization. Therefore, an improved superconducting TSV device and a corresponding manufacturing method are required to provide superconducting and thermally conductive via paths, accommodate higher current densities and lower losses, and provide dual operating temperature capabilities. The present embodiment relates to a superconducting silicon through-via (TSV) and a method for manufacturing the same. Various methods describe a manufacturing process for a superconducting TSV having a core made of a conductive material and an outer layer made of a superconducting material. The method includes the step of forming two electrically conductive channels separated by an insulating layer. The present specification also describes a component that is the result of such a manufacturing process. The TSV and the method for manufacturing the same described herein may be beneficial for enabling three-dimensional integration of superconducting circuits with higher circuit densities than conventional methods. In various embodiments, hybrid Cu/NbTiN metallization on a silicon interposer may enable the realization of a device comprising a thermally isolated heterogeneous system having dual operating temperatures. As one example, the TSV and the method described herein can effectively resolve communication bottlenecks and/or computational limitations. In such cases, the embodiments disclosed in this specification enable the implementation of superconducting digital (SCD) artificial intelligence (AI) and other high-performance computing (HPC) systems. In particular, SCD is a computer hardware technology aimed at providing sustainable growth for the execution of large-scale, advanced AI models. Thanks to enhanced power efficiency, computational density, and interconnect bandwidth, SCD delivers computation while significantly reducing cost, form factor, and power consumption. SCD applications can drive the development of technologies that enable packaging with 300 GHz of analog bandwidth per wire between die and board, wires with virtually no dissipation or dispersion up to hundreds of GHz frequencies, active devices with picosecond (ps) time scales and sub-attojoule energy scales, and quantum-accurate encoding of digital information. In SCD, fundamental energy dissipation per switching event does not depend on the manufacturing node, unlike in CMOS, but is instead determined by thermal noise. Therefore, SCD is the only digital technology that operates at thermodynamic limits while supporting high clock speeds of tens of GHz on a relaxed 30nm lithography node. Superconducting architectures provide 20 times higher clock speeds with 100 times less power on-chip compared to conventional circuits, and offer 10,000 times higher energy efficiency for inter-chip interconnects at on-chip clock speeds. Cryogenic cooling is applied volumetrically across the entire system rather than to individual dies, enabling very high packaging densities as all components of an ExaFlop-scale system are located physically and electrically close together. This technology supports heterogeneous architectures and enables high-density packaging through die stacking that includes both memory and computation. High computational density and interconnectivity eliminate communication bottlenecks between AI cores physically distributed across multiple chips and boards. A key differentiator is the ability to access DRAM across all boards simultaneously. As interconnect structures increasingly resemble the human brain, these architectures enable transparent data movement, faster learning, and smarter models. Furthermore, SCD is revolutionizing the AI market by redefining ExaScale servers that deliver data center-level performance, enabling low-latency real-time data applications by eliminating computational bottlenecks associated with reinforcement learning, multitasking learning, and near-edge data processing. By supporting these workloads, the growth of the AI market will be