KR-20260066771-A - Method and device for processing computational tasks

Abstract

The present invention provides a method and apparatus for processing computational tasks. The method comprises receiving a computational task including an original version field, modifying the original version field to obtain a plurality of modified version fields, and performing a hash operation on the computational task based on the plurality of modified version fields to generate a plurality of intermediate state values, wherein the plurality of intermediate state values are used in a Proof of Work (PoW) operation. By using the method, the objective of improving computational efficiency can be achieved by increasing the computational space for hash operations and decreasing the frequency of task reception, and the objective of lowering power consumption can be achieved by reducing the computational hardware area.

Inventors

• 한 종이
• 리 즈빈
• 장 난겅

Assignees

• 카난 크리에이티브 (에스에이치) 컴퍼니 리미티드

Dates

Publication Date

20260512

Application Date

20240614

Priority Date

20230908

Claims (20)

1. In terms of the method for handling computational tasks, Receiving an operation task including an original version field and performing a processing operation, but including A method for processing computation tasks, wherein the above processing operation involves changing the original version field to obtain a plurality of changed version fields, and performing a hash operation for each computation task based on the plurality of changed version fields to generate a plurality of intermediate state values for a PoW (Proof of Work) operation.
2. In paragraph 1, A method for processing computational tasks, wherein the above processing operation is performed repeatedly, and the modified version fields in the n+1th processing operation are different from any modified version fields in the 1st to nth processing operations.
3. In paragraph 1 or 2, A method for processing an operation task, further comprising receiving another operation task and performing the processing operation based on the original version field of the other operation task.
4. In any one of paragraphs 1 through 3, A method for processing computational tasks, wherein the original version field comprises a fixed portion, a soft fork voting portion, and a residual portion, and the residual portion is a portion used to modify the original version field to obtain the plurality of modified version fields.
5. In paragraph 4, A method for processing a computational task, wherein the bits of the remaining portion are changed in a random or predetermined order to obtain the plurality of changed version fields by changing the original version field.
6. In paragraph 4 or 5, A method for processing computational tasks, wherein the original version field is composed of 32 bits and the remaining portion is composed of 16 bits.
7. In any one of paragraphs 1 through 6, A method for processing a computation task, wherein the above computation task further includes a message field comprising a first region of a preceding block hash and a Merkle root hash.
8. In any one of paragraphs 1 through 7, Obtaining multiple intermediate state sub-values based on each intermediate state value; and A method for processing an operation task, further comprising outputting a serial data stream composed of a plurality of intermediate state sub-values for the above PoW operation.
9. In paragraph 8, A method for processing computational tasks, wherein the above plurality of intermediate state sub-values are obtained by dividing each of the above intermediate state values.
10. In Article 8 or 9, A method for processing computational tasks, wherein each intermediate state value is composed of 256 bits and each intermediate state lower value is composed of 32 bits.
11. In any one of paragraphs 1 through 10, The above operation task further includes a message field, and Generating multiple intermediate state values by performing a respective hash operation for the operation task based on the multiple modified version fields mentioned above, A method for processing computational tasks, comprising combining each modified version field with the message field to obtain each first block header section, and performing a hash operation based on each first block header section to generate each intermediate state value.
12. In Paragraph 11, A method for processing computation tasks, wherein each first block header section is divided into a plurality of first block header subsections, and a hash operation is performed based on a serial data stream composed of the plurality of first block header subsections of each first block header section to generate each intermediate state value.
13. In Article 11 or Article 12, A method for processing computational tasks, wherein each modified version field is combined with the message field based on the sequence values of the plurality of modified version fields to obtain each first block header section.
14. In Paragraph 13, A method for processing an operation task, wherein a pulse level corresponding to each sequence value is output, and in response to the pulse level, a modified version field corresponding to each sequence value and a message field are latched into a first block header section.
15. In paragraph 13 or 14, A method for processing an operation task, wherein a hash operation is performed on the m-th first block header section to generate each intermediate state value, and then the (m+1)-th modified version field is combined with the message field to obtain the (m+1)-th first block header section.
16. In paragraph 1, A method for processing a computation task, further comprising obtaining a PoW result value by performing a hash operation based on each of the plurality of intermediate state values and a second block header section of the computation task, wherein the second block header section includes a second region of a Merkle root hash, a timestamp, a target value, and a nonce.
17. In Paragraph 16, Performing each hash operation based on each of the above plurality of intermediate state values and the second block header section of the operation task is, Performing a first expansion operation on the second block header section to obtain a first expansion result; Performing a first compression operation based on each of the above plurality of intermediate state values and the above first expansion result to obtain each of the first compression results; Performing a second expansion operation based on each first compression result to obtain each second expansion result; and A method for processing computational tasks, comprising obtaining the PoW result value by performing a second compression operation based on each second expansion result.
18. In paragraph 1, A method for processing computation tasks, wherein the above plurality of intermediate state values are generated in a high-voltage domain and shifted from the high-voltage domain to a low-voltage domain for the PoW operation.
19. In any one of paragraphs 1 through 18, The above plurality of intermediate state values are generated in the upper region of the chip, a method for processing computational tasks.
20. In any one of paragraphs 1 through 19, A method for processing computational tasks where each hash operation is a SHA-256 operation.

Description

Method and device for processing computational tasks The present application claims priority to Chinese patent application No. 202311161624.7, filed on September 8, 2023, titled "Method and apparatus for processing computational tasks," the disclosure of said application is incorporated by reference into this specification. The present disclosure relates to the field of computational processing technology, and more specifically to a method and apparatus for processing computational tasks. This section is intended to provide background or context for the embodiments of the disclosure described in the claims. The description in this specification is not to be recognized as prior art by being included in this section. Proof of Work (PoW) is a consensus mechanism used for specific cryptographic operations, the main feature of which is that a large number of hash operations must be performed to find a valid hash value under specific difficulty conditions, which is also known as block operations. This basically involves performing multiple SHA-256 operations on a given block header to produce hash values that satisfy the expected difficulty. As illustrated in FIG. 1, the block header used in the cryptographic algorithm includes a 4-byte version; a 32-byte preceding block hash; a 32-byte Merkle root hash; a 4-byte timestamp; a 4-byte target value; and a 4-byte nonce. The block header is divided into two parts. The first part includes the 4-byte version field, the 32-byte preceding block hash field, and the first 28 bytes of the Merkle root hash field (the first region of the Merkle root hash). The second part includes the remaining 4 bytes of the Merkle root hash field (the second area of the Merkle root hash), a 4-byte timestamp field, a 4-byte difficulty target value field, and a 4-byte nonce field. The cryptographic algorithm is specified to first perform a SHA-256 operation on the first part to generate an intermediate state value, then perform a SHA-256 operation again on the intermediate state value and the second part, and then perform a final SHA-256 operation on the result to obtain a single operation result. In conventional block operations, the version, preceding block hash, and difficulty target value fields are all fixed, so the nonce must be repeatedly changed for the operation. However, the nonce is only 4 bytes, allowing only 2³² operations. Therefore, the Merkle root hash is generally changed to provide a larger search space. Referring again to the block header structure of FIG. 1, the Merkle root hash spans two parts of the header, and the approach of the conventional technology generally performs a massive hash collision search to identify multiple block headers where the last 4 bytes of the Merkle root hash are identical, in order to maximize computational efficiency and reduce power consumption. However, identifying such Merkle root hashes where the last 4 bytes are identical by performing a hash collision search is computationally expensive and may not be supported. Therefore, methods to implement PoW computation with cost reduction and low power consumption remain a challenge to be addressed. Other advantages and benefits of the present disclosure will become apparent to those skilled in the art by reading the detailed description of the exemplary embodiments below. The drawings are for the purpose of illustrating exemplary embodiments only and should not be construed as a limitation to the present disclosure. Additionally, throughout the drawings, the same reference numerals indicate the same components. In the drawings: Figure 1 is a schematic diagram showing the structure of a block header of the prior art. FIG. 2 is a schematic flowchart of a PoW operation method according to one embodiment of the present disclosure. FIG. 3 is a schematic structural diagram of a computation chip according to one embodiment of the present disclosure. FIG. 4 is a schematic diagram showing the transmission state of an intermediate state value according to one embodiment of the present disclosure. FIG. 5 is a schematic flowchart of a PoW operation method according to another embodiment of the present disclosure. FIG. 6 is a schematic structural diagram of a PoW computing device according to one embodiment of the present disclosure. FIG. 7 is a schematic structural diagram of a computation module of a PoW computation device according to one embodiment of the present disclosure. FIG. 8 is a schematic structural diagram of a subsequent stage computation core according to one embodiment of the present disclosure. In a drawing, identical or corresponding reference numbers indicate identical or corresponding parts. Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. It should be understood that while exemplary embodiments of the present disclosure are illustrated in the drawings, the present disclosure may be embodied in various forms