Search

KR-20260066783-A - Integrated interrupt control method and device based on LRO timeout and interrupt ITR timeout

KR20260066783AKR 20260066783 AKR20260066783 AKR 20260066783AKR-20260066783-A

Abstract

The present invention provides an integrated interrupt control method and apparatus based on LRO timeouts and interrupt ITR timeouts, wherein the method comprises the steps of: mapping an interrupt request from a DMA receive queue to an interrupt vector and reusing the ITR timeout counter of the interrupt vector; when the ITR timeout counter reaches a first time interval, inversely mapping one LRO timeout pulse to the DMA receive queue to cause the DMA receive queue to stop aggregating the current data stream and writing the aggregated data stream to host memory; and when the ITR timeout counter reaches a second time interval, reporting an interrupt request generated in the DMA receive queue to the host side. The technical solution of the present invention combines interrupt timeouts and receive queue LRO timeouts to reduce CPU utilization, save chip resources, and reduce power consumption.

Inventors

  • 둥수린
  • 두신
  • 중스펑
  • 진쥔하오
  • 랴오위엔

Assignees

  • 우시 스타즈 마이크로 시스템 테크놀로지스 컴퍼니 리미티드

Dates

Publication Date
20260512
Application Date
20241012
Priority Date
20231017

Claims (10)

  1. As an integrated interrupt control method based on Large Receive Offload (LRO) timeout and time-based interrupt limit timeout, A step of mapping an interrupt request from a Direct Memory Access (DMA) receive queue to an interrupt vector, and reusing a time-based interrupt limit timeout counter of said interrupt vector; When the time-based interrupt limit timeout counter reaches the first time interval, a step of inversely mapping one LRO timeout pulse to the DMA receive queue to cause the DMA receive queue to stop aggregating the current data stream and writing the aggregated data stream to host memory; and A method characterized by including the step of reporting an interrupt request generated in the DMA receive queue to the host side when the time-based interrupt limit timeout counter reaches a second time interval.
  2. In Article 1, A method characterized in that the sum of the first time interval and the second time interval is a time-based interrupt limit timeout interval.
  3. In Article 1, The above step of writing the aggregated data stream to host memory is, A method characterized by further including the step of writing the received data aggregated from the DMA receiving queue and the corresponding descriptors to host memory via DMA.
  4. In Paragraph 3, After the above step of writing the aggregated data stream to host memory, the method, A method characterized by further including the step of generating an interrupt request and transmitting the interrupt request to an interrupt processing module so that the DMA receiving queue automatically starts aggregating a new data stream.
  5. In Article 1, The above method is, A method characterized by further including the step of dynamically configuring the second time interval according to the link delay state to ensure that the DMA receiving queue already writes the aggregated data packet to the host memory before reporting the interrupt request.
  6. As an integrated interrupt controller based on Large Receive Offload (LRO) timeouts and time-based interrupt limit timeouts, A mapping unit that maps an interrupt request from a Direct Memory Access (DMA) receive queue to an interrupt vector and reuses a time-based interrupt limit timeout counter of said interrupt vector; A reverse mapping unit that, when the time-based interrupt limit timeout counter reaches a first time interval, reverse maps one LRO timeout pulse to the DMA receive queue to cause the DMA receive queue to stop aggregating the current data stream and writes the aggregated data stream to host memory; and A device characterized by including an interrupt unit that reports an interrupt request generated in the DMA receive queue to the host side when the time-based interrupt limit timeout counter reaches a second time interval.
  7. A device according to claim 6, characterized in that the sum of the first time interval and the second time interval is a time-based interrupt limit timeout interval.
  8. In Paragraph 6, The above-mentioned reverse mapping unit also, A device characterized by writing aggregated received data and corresponding descriptors from the above DMA receiving queue to host memory via DMA.
  9. In Paragraph 8, The above-mentioned reverse mapping unit also, A device characterized by generating an interrupt request and transmitting the interrupt request to an interrupt processing module so that the DMA receiving queue automatically starts aggregating a new data stream.
  10. In Paragraph 6, A device characterized by further including a configuration unit that dynamically configures the second time interval according to the link delay state to ensure that the DMA receive queue already writes the aggregated data packet to the host memory before reporting the interrupt request.

Description

Integrated interrupt control method and device based on LRO timeout and interrupt ITR timeout The present invention claims priority to a Chinese application with application number 202311344548.3, filing date October 17, 2023, and patent title “Integrated interrupt control method and apparatus based on LRO timeout and interrupt ITR timeout”, the contents of said application incorporated herein by reference. The present invention relates to the field of network transmission technology, and in particular to an integrated interrupt control method and apparatus based on LRO timeout and interrupt ITR timeout. In networks, information is generally transmitted in units of data packets. The maximum size of a data packet that can be transmitted is called the Mobile Transfer Unit (MTU), and it is measured in bytes. RFC standards define the default MTU for Ethernet as 1500 bytes. If a data packet that software intends to transmit exceeds the above MTU size, the TCP Segmentation Offload (TSO) technology splits the data packet according to the MTU and transmits the split data packet fragments to the receiving end through the network. Depending on the transmission direction, the receiving path of the network interface card chip uses a technique (LRO, Large Receive Offload) that aggregates multiple data packet fragments (TCP fragments). To prevent a single very long packet from being aggregated, conventional LRO uses a timeout counter within each receive queue; when a timeout occurs, the aggregation of the current data stream is stopped, the aggregated data is written to host memory, and the descriptor is sent back to the host. An interrupt is then generated to notify the host software. The purpose of this technique is to improve network transmission performance by merging data packets received from the network interface card chip before delivering them to the operating system, thereby reducing the number of CPU interrupts and decreasing the CPU load. In addition, the network interface card interrupt module can prevent excessive interrupt reporting to the host through the Time-Based Interrupt Throttling (ITR) function. Interrupts are reported to the host software only after the ITR counter times out. For example, bandwidth can be saved and interrupt suppression effects improved by determining whether a threshold set in the software is exceeded using the difference between the interrupt timestamp and the system time. However, the aforementioned prior art has the following disadvantages. First, when the LRO function is enabled, timeout counters must be used for each receive queue and each interrupt vector to prevent data packets from occupying LRO aggregation stream resources for a long time due to a lack of subsequent data fragments, or to prevent the logic hardware from generating very long data packets by continuously aggregating. Both the interrupt module and the LRO module consume significant resources and power as numerous counters operate constantly. Second, to improve network processing performance, it is ideal for the software to immediately receive an interrupt and process LRO data after the LRO timeout and aggregation stop. However, synchronization is impossible because the LRO timeout and the interrupt times reported by the interrupt module are not synchronized. If aggregation is suspended for a long time due to an LRO timeout, and multiple interrupts time out before the LRO timeout of the corresponding queue occurs once, the actual logic may have processed some of the LRO data, but the interrupt reported to the host software in the previous call failed to notify the host that there was LRO data available to process. The interrupt module sends an interrupt request only after an LRO timeout and notifies the software of the processed LRO data after waiting for the interrupt to time out; this can result in a situation where the CPU has idle time but is unable to process data. Conversely, in queues with short LRO timeouts, multiple LRO timeouts may occur before an interrupt timeout takes place. Both of these scenarios lead to a situation where the CPU must suddenly process a large amount of data. To more clearly explain the embodiments of the present invention or the technical solutions of the prior art, the drawings used in describing the embodiments of the present invention or the prior art are briefly introduced below. The drawings described below are merely some embodiments of the present invention. A person skilled in the art would be able to obtain other drawings based on these drawings without any significant inventive effort. FIG. 1 is a flowchart of an integrated interrupt control method based on LRO timeout and interrupt ITR timeout according to an embodiment of the present invention. FIG. 2 is a block diagram of an integrated interrupt control method based on LRO timeout and interrupt ITR timeout according to an embodiment of the present invention. FIG. 3 is a flowchart showing how an LRO queue reuses an