KR-20260066796-A - Membrane formation method and semiconductor manufacturing device

KR20260066796AKR 20260066796 AKR20260066796 AKR 20260066796AKR-20260066796-A

Abstract

The increase in wiring resistance of the wiring material embedded inside the pattern is suppressed. When forming metal wiring on a silicon-based wafer (W), a Zr film (27) is formed inside a pattern (26) that is opened in the insulating film (25) of the wafer (W), the formed Zr film (27) is etched to adjust the film thickness of the Zr film (27), a Ti film (28) is formed on the Zr film (27) using TiCl4 gas, and the same TiCl4 gas is used for the etching of the Zr film (27).

Inventors

이구치 유수케
나루시마 겐사쿠
고바야시 다카시
사쿠마 다카시

Assignees

도쿄엘렉트론가부시키가이샤

Dates

Publication Date: 20260512
Application Date: 20240821
Priority Date: 20231002

Claims (18)

A film formation method for forming metal wiring on a silicon-based substrate to be processed, wherein a metal film is formed inside a pattern that is opened in an insulating film of said substrate to be processed, and a contact portion made of metal silicide is formed at the bottom of said pattern. A first film formation process for forming a first metal film inside the above pattern, and A film thickness adjustment process for adjusting the film thickness of the first metal film formed above, and It includes a second film formation process for forming a second metal film on the first metal film using a raw material gas, and A film formation method in which the first metal film formed above is etched using the source gas in the above film thickness adjustment process.
In paragraph 1, A film deposition method in which the film thickness adjustment process and the second film deposition process are repeated to deposit the second metal film on the first metal film.
In paragraph 2, A film deposition method that realizes the repetition of the above film thickness adjustment process and the above second film deposition process by applying pulses of high-frequency voltage.
In paragraph 1, A film deposition method for depositing the second metal film on the first metal film without repeating the film thickness adjustment process and the second film deposition process.
In paragraph 1, A film formation method in which the raw material gas is not plasmafied in the film thickness adjustment process above, and the raw material gas is plasmafied in the second film formation process above.
In paragraph 1, A film formation method in which either the film thickness adjustment process or the second film formation process plasmas the source gas.
In paragraph 1, An oxide film removal process for removing an oxide film formed on the surface of the substrate to be processed, and A film formation method comprising, in addition to, a wiring process of embedding a metal, which is a wiring material, on the second metal film within the above pattern.
In Paragraph 7, A film deposition method comprising, further comprising, a cleaning process for removing etching residue of the first metal film between the second film deposition process and the wiring process.
In paragraph 1, A method for forming a film, wherein the first metal film comprises any one of zirconium, molybdenum, and hafnium.
In paragraph 1, A film formation method in which the second metal film comprises titanium.
In paragraph 1, A film formation method in which the above-mentioned raw gas is a gas of a chloride containing titanium or a gas of a halide containing titanium.
In Paragraph 11, A method for forming a film, wherein the above raw gas is also a gas comprising at least one of tungsten chloride, tungsten hexachloride, molybdenum chloride, molybdenum hexachloride, hafnium tetrachloride, and zirconium tetrachloride.
In paragraph 1, The above pattern is a membrane formation method, which is a contact hole or trench.
A semiconductor manufacturing apparatus for forming metal wiring on a silicon-based substrate to be processed, wherein a metal film is formed inside a pattern that is opened in an insulating film of said substrate to be processed, and a contact portion formed at the bottom of said pattern is made of metal silicide. A first film forming part that forms a first metal film inside the above pattern, and It includes a second film formation section that forms a second metal film on the first metal film formed above using a raw material gas, and The above second film formation unit is a semiconductor manufacturing apparatus that adjusts the film thickness of the first metal film formed using the above raw material gas.
In Paragraph 14, A semiconductor manufacturing apparatus comprising a second film-forming unit for plasmafiing the raw material gas.
In Paragraph 14, A semiconductor manufacturing apparatus in which the first film portion and the second film portion are connected to the same vacuum carrier system.
In Paragraph 14, A semiconductor manufacturing apparatus in which the first film-forming part has an introduction part for the raw material gas and thus serves as the second film-forming part.
In Paragraph 14, The semiconductor manufacturing apparatus wherein the second film-forming unit performs a cleaning treatment on the substrate to be treated to remove etching residue of the first metal film.

Description

Membrane formation method and semiconductor manufacturing device The present disclosure relates to a film formation method and a semiconductor manufacturing apparatus. For example, in a logic IC as a semiconductor device, titanium (Ti) is used as a source or drain contact material. Titanium is deposited on the inner wall or bottom surface of a trench or contact hole, which is a pattern formed in an insulating film (see, for example, Patent Document 1). Then, a metal of low resistance material, for example ruthenium (Ru), is embedded in the pattern as a wiring material. FIG. 1 is a plan view for explaining an example of the configuration of a semiconductor manufacturing apparatus according to one embodiment of the technology related to the present disclosure. FIG. 2 is an enlarged cross-sectional view of an example of a pattern area in a wafer in which wiring material is embedded after various processing is performed in the semiconductor manufacturing apparatus of FIG. 1. FIG. 3 is a flowchart (an example) for explaining the tabernacle method according to the present embodiment. FIG. 4 is a process diagram (an example) for explaining a method for forming a tabernacle according to the present embodiment. FIG. 5 is a flowchart (example) for explaining a modified example of the tabernacle method according to the present embodiment. FIG. 6 is a process diagram (example) for explaining a modified example of the membrane formation method according to the present embodiment. FIG. 7 is a plan view for explaining the configuration of a modified example of a semiconductor manufacturing device according to the present embodiment. In recent years, zirconium (Zr) has been considered a promising candidate as a contact material, and when Zr is used, it is laminated with Ti on the inner walls or bottom surfaces of the pattern. However, there is a concern that if the Zr film becomes thicker inside the pattern, the volume of the internal wiring material of the pattern decreases as a result, leading to an increase in wiring resistance. In this regard, the technology of the present disclosure adjusts the thickness of the Zr film by etching the Zr film after forming the Zr film inside the pattern. Hereinafter, an embodiment of the technology according to the present disclosure will be described with reference to the drawings. FIG. 1 is a plan view for explaining an example of the configuration of a semiconductor manufacturing apparatus according to the present embodiment. In FIG. 1, the semiconductor manufacturing apparatus (10) has a COR (Chemical Oxide Removal) chamber (11) for performing COR treatment and a PHT (Post Heat Treatment) chamber (12) for performing PHT treatment. Additionally, the semiconductor manufacturing apparatus (10) has a Zr film chamber (13) (first film chamber) for performing zirconium (Zr) film deposition treatment and a Ti film chamber (14) (second film chamber) for performing titanium (Ti) film deposition treatment. The COR chamber (11) and the PHT chamber (12) are connected to the first transfer module (16), and the Zr film chamber (13) and the Ti film chamber (14) are connected to the second transfer module (17). Additionally, the first transfer module (16) is connected to the loader module (19) via the load lock module (18). Furthermore, the arrangement of each module is not limited to this, and the COR chamber (11) and the PHT chamber (12) may be connected to the second transfer module (17), or the Zr film chamber (13) and the Ti film chamber (14) may be connected to the first transfer module (16). A loader module (19) is provided with a plurality of load ports (20), and each load port (20) is equipped with a container for accommodating a plurality of wafers, such as a FOUP (not shown). Additionally, the first transfer module (16) and the second transfer module (17) are connected via a wafer receiving unit (21). In the semiconductor manufacturing device (10), the loader module (19), the first transfer module (16), and the second transfer module (17) each contain a transport robot (not shown). Each transport robot transports a wafer between the COR chamber (11), the PHT chamber (12), the Zr film deposition chamber (13), the Ti film deposition chamber (14), and each load port (20). The loader module (19) is an atmospheric transport system or a nitrogen transport system, and its interior is maintained at atmospheric pressure. The first transfer module (16) or the second transfer module (17) is a vacuum transport system, and its interior is depressurized to near vacuum. The load lock module (18) is configured to switch its interior to atmospheric pressure or near vacuum. When a wafer is transported between the first transfer module (16) and the loader module (19), the load lock module (18) enables the transport of the wafer without changing the internal pressure of the first transfer module (16) or the loader module (19) by switching the internal pressure. Additionally, the COR chamber (11), PHT chambe