KR-20260066852-A - SEMICONDUCTOR DEVICE INCLUDING THROUGH VIA

Abstract

A semiconductor device according to embodiments of the present invention comprises: a first structure having a memory region; and a second structure having a peripheral circuit region that overlaps vertically with the first structure and overlaps vertically with the memory region, wherein the first structure comprises memory cells disposed within the memory region; and a cell routing wiring structure electrically connected to the memory cells, and the second structure comprises: a semiconductor body; a rear insulating layer disposed on the lower surface of the semiconductor body; a first peripheral transistor comprising a first peripheral source/drain disposed within a first peripheral active region of the semiconductor body, a second peripheral source/drain, a first peripheral channel region between the first and second peripheral source/drains, and a first peripheral gate disposed on the first peripheral channel region; a first penetrating insulating pattern penetrating the semiconductor body; and a device isolation pattern having a lower surface disposed at a higher level than the lower surface of the semiconductor body within the semiconductor body and spaced apart horizontally from the first penetrating insulating pattern. and includes a through-via that penetrates the first through-insulating pattern and the rear insulating layer and is electrically connected to the cell routing wiring structure, wherein the first through-insulating pattern may include a first insulating pattern comprising a first portion adjacent to the rear insulating layer and a second portion disposed on the first portion, and a second insulating pattern disposed between the side of the second portion of the first insulating pattern and the semiconductor body.

Inventors

• 이정렬
• 권동훈

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20241105

Claims (10)

1. A first structure having a memory area; and It includes a second structure having a peripheral circuit region that overlaps vertically with the first structure and overlaps vertically with the memory region, The above-mentioned first structure is, Memory cells disposed within the above memory region, each comprising a vertical channel transistor and an information storage structure; and It includes a cell routing wiring structure electrically connected to the memory cells, and The above second structure is, Semiconductor body; Rear insulating layer below the above semiconductor body; A device isolation pattern having a peripheral active region of the semiconductor body and a lower surface positioned at a higher level than the lower surface of the semiconductor body; A first penetrating insulating pattern penetrating the semiconductor body; A second penetrating insulating pattern penetrating the semiconductor body below the device isolation pattern among the above device isolation pattern and the above semiconductor body; A peripheral transistor comprising a first peripheral source/drain disposed within the above peripheral active region, a second peripheral source/drain, a peripheral channel region between the first and second peripheral source/drains, and a peripheral gate disposed on the above peripheral channel region; and A semiconductor device comprising a through-via that penetrates the first through-insulating pattern and is electrically connected to the cell routing wiring structure.
2. In Article 1, A semiconductor device in which the lower surface of the semiconductor body, the lower surface of the first through-insulating pattern, and the lower surface of the second through-insulating pattern form a coplanar plane.
3. In Article 1, The first penetrating insulating pattern is, A first insulating pattern comprising a first portion adjacent to the rear insulating layer and a second portion extending from the first portion; and A semiconductor device comprising a second insulating pattern disposed between the side of the second portion of the first insulating pattern and the semiconductor body on the first portion of the first insulating pattern.
4. In Paragraph 3, The upper surface of the first portion of the first insulation pattern includes a first region to which the second portion of the first insulation pattern extends and a second region excluding the first region, and The second region of the first part above is a semiconductor device in contact with the semiconductor body.
5. In Article 1, The lower surface of the above-mentioned first penetrating insulating pattern has a first width in a first direction, and A semiconductor device having a lower surface of the second through-insulating pattern having a second width smaller than the first width in the first direction.
6. In Article 1, The second penetrating insulating pattern is, A third insulation pattern comprising a third portion adjacent to the rear insulation layer and a fourth portion extending from the third portion; and A semiconductor device comprising a fourth insulating pattern disposed between the side of the fourth part of the third insulating pattern and the semiconductor body on the third part of the third insulating pattern.
7. A first structure having a memory area; and It includes a second structure having a peripheral circuit region that overlaps vertically with the first structure and overlaps vertically with the memory region, The above-mentioned first structure is, Memory cells disposed within the above memory area; and It includes a cell routing wiring structure electrically connected to the memory cells, and The above second structure is, Semiconductor body; A rear insulating layer disposed on the lower surface of the semiconductor body; A first peripheral transistor comprising a first peripheral source/drain disposed within a first peripheral active region of the semiconductor body, a second peripheral source/drain, a first peripheral channel region between the first and second peripheral source/drains, and a first peripheral gate disposed on the first peripheral channel region; A first penetrating insulating pattern penetrating the semiconductor body; A device isolation pattern having a lower surface disposed at a higher level than the lower surface of the semiconductor body within the semiconductor body, and spaced horizontally from the first through-insulating pattern; and It includes a through-via that penetrates the first through-insulating pattern and the rear insulating layer and is electrically connected to the cell routing wiring structure, A semiconductor device comprising a first through-insulating pattern, the first insulating pattern comprising a first portion adjacent to the rear insulating layer and a second portion disposed on the first portion, and a second insulating pattern disposed between the side of the second portion of the first insulating pattern and the semiconductor body.
8. In Article 7, The above second structure is, The second peripheral transistor further comprises a third peripheral source/drain disposed within a second peripheral active region of the semiconductor body, a fourth peripheral source/drain, a second peripheral channel region between the third and fourth peripheral source/drains, and a second peripheral gate disposed on the second peripheral channel region of the second peripheral active region. A semiconductor device in which the device isolation pattern is disposed between the first peripheral transistor and the second peripheral transistor.
9. In Article 7, The second structure further includes a second penetrating insulating pattern penetrating the semiconductor body below the device isolation pattern among the device isolation pattern and the semiconductor body. The second penetrating insulating pattern is, A third insulation pattern comprising a third portion adjacent to the rear insulation layer and a fourth portion extending from the third portion; and A semiconductor device comprising a fourth insulating pattern disposed between the side of the fourth part of the third insulating pattern and the semiconductor body on the third part of the third insulating pattern.
10. A first structure having memory cells disposed in a memory region and a cell routing wiring structure electrically connected to said memory cells; and It includes a second structure having a peripheral circuit region that overlaps vertically with the first structure and overlaps vertically with the memory region, The above second structure is, Semiconductor body; A device isolation pattern that defines peripheral active regions of the semiconductor body; A first penetrating insulating pattern penetrating the semiconductor body; A peripheral transistor comprising a first peripheral source/drain disposed within the above peripheral active region, a second peripheral source/drain, a peripheral channel region between the first and second peripheral source/drains, and a peripheral gate disposed on the above peripheral channel region; and It includes a through-via that penetrates the first through-insulating pattern and is electrically connected to the cell routing wiring structure, A semiconductor device comprising a first insulating pattern having a first portion having a lower surface that forms a co-plane with the lower surface of the semiconductor body and a second portion disposed on the first portion, and a second insulating pattern on the side of the second portion of the first insulating pattern.

Description

Semiconductor device including through-via The present invention relates to a semiconductor device comprising through-vias. Research is underway to reduce the size of the components constituting semiconductor devices and improve their performance. For example, in DRAM, research is being conducted to reliably and stably form reduced-size components; however, as the size of these components decreases, the performance of the semiconductor device is degrading. FIG. 1 is a schematic perspective view of a semiconductor device according to embodiments of the present invention. FIG. 2a is a schematic perspective view of a bank of semiconductor devices of FIG. 1. FIG. 2b is a circuit diagram according to one embodiment of a first structure within a memory cell array region of a semiconductor device of FIG. 1. FIG. 3a is a cross-sectional view showing an embodiment along the line I-I' of the semiconductor device of FIG. 2. FIG. 3b is a cross-sectional view showing an embodiment along the line II-II' of the semiconductor device of FIG. 2. FIG. 4 is a partial enlarged view according to one embodiment of the semiconductor device shown in FIG. 3a. FIGS. 5 to 9 are enlarged views of some embodiments of the semiconductor device shown in FIG. 3a. FIGS. 10a to 10j are drawings illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 11a to 11e are drawings illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted. FIG. 1 is a schematic perspective view of a semiconductor device according to embodiments of the present invention. FIG. 2a is a schematic perspective view of a bank of the semiconductor device of FIG. 1. FIG. 2b is a circuit diagram according to one embodiment of a first structure within a memory cell array region of the semiconductor device of FIG. 1. Referring to FIGS. 1 and FIGS. 2a, the semiconductor device (1) may include a first structure (ST1) and a second structure (ST2) that overlaps vertically with the first structure (ST1). The second structure (ST2) may be placed on the first structure (ST1). The first structure (ST1) may be a first chip structure including memory cells, and the second structure (ST2) may be a second chip structure including peripheral circuits capable of operating the memory cells. The first structure (ST1) and the second structure (ST2) may be formed by joining through a bonding process such as a wafer bonding process. Accordingly, the first structure (ST1) may be joined to the second structure (ST2) in contact with it. A semiconductor device (1) may include a plurality of banks (BA) and a peripheral circuit region (PERI). The peripheral circuit region (PERI) may include a first peripheral region (PERI1) within a first structure (ST1) and a second peripheral region (PERI2) within a second structure (ST2). The peripheral circuit region (PERI) may be a peripheral circuit region in which peripheral circuits for input/output of data or commands, or input of power/ground, are arranged. Each of the plurality of banks (BA) may include a first bank area (BA1) within the first structure (ST1) and a second bank area (BA2) within the second structure (ST2). Referring to FIGS. 2a and 2b, a first bank region (BA1) within a first structure (ST1) may include memory cell array regions (CA). The memory cell array regions (CA) may include memory cells. The memory cell array regions (CA) may be arranged along a first direction (X direction) and a second direction (Y direction). Each of the memory cell array regions (CA) may include memory cells (MC) arranged along the first direction (X direction) and the second direction (Y direction), word lines (WL) connected to the memory cells (MC) and extending in the first direction (X), and bit lines (BL) connected to the memory cells (MC) and extending in the second direction (Y). Each of the memory cells (MC) may include a cell transistor (cTR) and an information storage structure (DS) capable of storing information. In memory such as DRAM, the information storage structure (DS) may be a cell capacitor capable of storing information. Each of the memory cell array regions (CA) may further include back gate lines (BG). Each of the back gate lines (BG) may be positioned between a pair of word lines (WL) that are adjacent to each other in a second direction (Y direction) among the word lines (WL). Each of the back gate lines (BG) may be positioned between the channel regions of the cell transistors (cTR). A second bank region (BA2) within a second structure (ST2) may include peripheral circuit regions (PC). The peripheral circuit regions (PC) may be arranged along a fir