KR-20260066924-A - SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package of the present disclosure comprises a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package disposed on the lower package, and an interposer substrate disposed between the lower package and the upper package and having an interposer hole formed to allow the lower semiconductor chip to pass through, wherein the upper package comprises an upper package substrate disposed on the interposer substrate and an upper semiconductor chip disposed on the upper package substrate, and the upper package substrate may comprise a first cavity surface located at a level higher than the lower surface of the upper package substrate, a second cavity surface connecting the lower surface of the upper package substrate and the first cavity surface, and a cavity formed by the first cavity surface and the second cavity surface.

Inventors

• 박기태
• 심종보
• 이장우

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20241105

Claims (10)

1. A lower package comprising a lower package substrate and a lower semiconductor chip disposed on the lower package substrate; and An upper package disposed on the lower package above; and It includes an interposer substrate disposed between the lower package and the upper package and having an interposer hole formed to allow the lower semiconductor chip to pass through, and The above upper package is, An upper package substrate disposed on the above interposer substrate; and It includes an upper semiconductor chip disposed on the upper package substrate, and The semiconductor package comprises an upper package substrate, a first cavity surface located at a higher level than the lower surface of the upper package substrate, a second cavity surface connecting the lower surface of the upper package substrate and the first cavity surface, and a cavity formed by the first cavity surface and the second cavity surface.
2. In Article 1, A semiconductor package in which at least a portion of the lower semiconductor chip is accommodated in the cavity and overlapped in a first direction parallel to the upper surface of the lower package substrate.
3. In Article 1, A semiconductor package in which at least a portion of the lower semiconductor chip is in contact with at least one of the first cavity surface or the second cavity surface.
4. In Article 1, It further includes a heat dissipation structure disposed on the lower semiconductor chip above, and A semiconductor package in which the above heat dissipation structure contacts at least one of the first cavity surface or the second cavity surface.
5. In Paragraph 4, The above heat dissipation structure includes a heat dissipation layer comprising a thermally conductive material, and A semiconductor package in which the heat dissipation layer contacts at least one of the first cavity surface or the second cavity surface.
6. In Article 5, A semiconductor package, wherein the heat dissipation structure further comprises a dummy structure disposed on the heat dissipation layer and in contact with at least one of the first cavity surface or the second cavity surface.
7. In Article 1, A semiconductor package in which, from a planar perspective, each of the cavity and the interposer hole has an area corresponding to the upper surface of the lower semiconductor chip.
8. A lower package comprising a lower package substrate and a lower semiconductor chip disposed on the lower package substrate; An interposer substrate disposed on the lower package and having an interposer hole formed to allow at least a portion of the lower semiconductor chip to pass through; and The upper package includes an upper package substrate disposed on the interposer substrate and an upper semiconductor chip disposed on the upper package substrate, and The upper package substrate above is, A wiring layer comprising a metal material; and It includes a cavity formed such that at least a portion of the wiring layer is exposed, and A semiconductor package in which the upper surface of the lower semiconductor chip is positioned to pass through the interposer hole and be received in the cavity.
9. In Article 8, A semiconductor package in which the lower semiconductor chip is in contact with at least a portion of the exposed wiring layer.
10. In Article 8, It further includes a heat dissipation structure disposed on the lower semiconductor chip, wherein heat generated from the lower semiconductor chip is transferred to the upper package substrate. A semiconductor package in which at least a portion of the above-mentioned heat dissipation structure is disposed within the above-mentioned cavity.

Description

Semiconductor Package The present disclosure relates to a semiconductor package. In small electronic devices such as mobile phones and tablet PCs, an application processor (AP) and memory can each be manufactured as a single System on Chip (SOC) and mounted on a system board. However, in this case, a modem System in Package (SIP) must be additionally mounted on the system board, which may limit the miniaturization of the electronic device. Meanwhile, Package-on-Package (PoP) structures, which stack APs and memory, are being used to miniaturize electronic devices and reduce their thickness. Methods are being researched to dissipate heat generated by the application processor (AP) to the outside of the semiconductor package within the Package-on-Package structure. FIG. 1 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure. FIG. 2 is an enlarged view of a portion of a semiconductor package according to some embodiments of the present disclosure. FIG. 3 is a diagram illustrating a heat dissipation path of a semiconductor package according to some embodiments of the present disclosure. FIG. 4 is a cross-sectional view illustrating the state before coupling of a lower package and an interposer substrate according to some embodiments of the present disclosure. FIG. 5 is a plan view illustrating the combined state of a lower package and an interposer substrate according to some embodiments of the present disclosure. FIG. 6 is a cross-sectional view illustrating a combined state of a lower package and an interposer substrate according to some embodiments of the present disclosure. FIG. 7 is a cross-sectional view illustrating an upper package according to some embodiments of the present disclosure. FIG. 8 is a drawing for explaining the state before the upper package, interposer substrate, and lower package of a semiconductor package are combined according to some embodiments of the present disclosure. FIGS. 9 to 11 are drawings for illustrating a semiconductor package according to some embodiments of the present disclosure. FIGS. 12 and FIGS. 13 are drawings for illustrating a semiconductor package according to some embodiments of the present disclosure. FIGS. 14 and FIGS. 15 are drawings for illustrating a semiconductor package according to some embodiments of the present disclosure. FIGS. 16 and 17 are drawings for illustrating a semiconductor package according to some embodiments of the present disclosure. A semiconductor package according to some embodiments of the present disclosure will be described in detail below with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure. FIG. 2 is an enlarged view illustrating a portion of a semiconductor package according to some embodiments of the present disclosure. FIG. 3 is a view illustrating a heat dissipation path of a semiconductor package according to some embodiments of the present disclosure. Referring to FIGS. 1 and FIGS. 2, a semiconductor package (1) according to some embodiments of the present disclosure may include a lower package (10), an interposer substrate (20), and an upper package (30). In the drawing, the left-right direction or horizontal direction may be a first direction (D1) parallel to the upper surface of the lower package substrate (100). Additionally, the up-down direction or vertical direction may be a second direction (D2) perpendicular to the upper surface of the lower package substrate (100). The lower package (10) may include a lower package substrate (100), a lower semiconductor chip (110), a conductive post (120), an underfill (130), and a lower molding layer (140). The lower package substrate (100) may be a substrate for connecting the lower semiconductor chip (110) of the lower package (10) and the upper package (30) to an external device. The lower package substrate (100) may be a printed circuit board (PCB) or a redistributed layer (RDL). In some embodiments, the printed circuit board may be a multilayer printed circuit board having a substrate base formed by stacking a plurality of base layers. In some embodiments, each of the plurality of base layers forming the substrate base may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, each of the plurality of base layers forming the substrate base may include at least one material selected from FR4 (Frame Retardant 4), tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, BT (Bismaleimidetriazine), Thermount, cyanate ester, polyimide, and liquid crystal polymer. The lower package substrate (100) may include a wiring pattern (100p). The wiring pattern (100p) may be disposed on the upper and lower surfaces of each of a plurality of base layers. The wiring pattern (100p) may be made of, for example, electrolytically deposited (ED) copper foil, rolled-ann