KR-20260066925-A - SEMICONDUCTOR DEVICE

Abstract

The semiconductor device of the present disclosure comprises a lower insulating layer including a first region and a second region, a first channel pattern stacked in a first direction on the first region and having a first width in a second direction intersecting the first direction - the first channel pattern includes a first lower channel pattern and a first upper channel pattern spaced apart from the first lower channel pattern in a first direction - a second channel pattern stacked in a first direction on the second region and having a second width greater than the first width in a second direction - the second channel pattern includes a second lower channel pattern and a second upper channel pattern spaced apart from the second lower channel pattern in a first direction - a first gate electrode surrounding the first channel pattern and a second gate electrode surrounding the second channel pattern, and a first lower source/drain pattern disposed on at least one side of the first lower channel pattern and a second lower source/drain pattern disposed on at least one side of the second lower channel pattern, wherein the angle between the sidewall of the first channel pattern and the upper surface of the lower insulating layer may be greater than the angle between the sidewall of the second channel pattern and the upper surface of the lower insulating layer.

Inventors

• 김다혜
• 박성일
• 박재현
• 윤철진

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20241105

Claims (10)

1. A lower insulating layer including a first region and a second region; A first channel pattern stacked in a first direction on the first region and having a first width in a second direction intersecting the first direction - the first channel pattern includes a first lower channel pattern and a first upper channel pattern spaced apart from the first lower channel pattern in the first direction -; A second channel pattern stacked in the first direction on the second region and having a second width greater than the first width in the second direction - the second channel pattern includes a second lower channel pattern and a second upper channel pattern spaced apart from the second lower channel pattern in the first direction -; A first gate electrode surrounding the first channel pattern and a second gate electrode surrounding the second channel pattern; and A first lower source/drain pattern disposed on at least one side of the first lower channel pattern and a second lower source/drain pattern disposed on at least one side of the second lower channel pattern Includes, A semiconductor device in which the angle between the sidewall of the first channel pattern and the upper surface of the lower insulating layer is greater than the angle between the sidewall of the second channel pattern and the upper surface of the lower insulating layer.
2. In Article 1, A semiconductor device in which, based on a third direction intersecting each of the first direction and the second direction, the width of the second lower source/drain pattern is greater than the width of the first lower source/drain pattern.
3. In Article 1, It further includes a first upper source/drain pattern disposed on one side of the first upper channel pattern and a second upper source/drain pattern disposed on one side of the second upper channel pattern, A semiconductor device in which the angle between the sidewall of the second upper source/drain pattern and the upper surface of the lower insulating layer is smaller than the angle between the sidewall of the first upper source/drain pattern and the upper surface of the lower insulating layer.
4. In Article 1, The first gate electrode includes a first lower gate electrode surrounding the first lower channel pattern, and The second gate electrode includes a second lower gate electrode surrounding the second lower channel pattern, and A semiconductor device in which, based on a third direction intersecting each of the first direction and the second direction, the width of the first lower gate electrode is greater than the width of the second lower gate electrode.
5. In Article 1, A first lower contact in contact with the first lower source/drain pattern; and It further includes a second lower contact that contacts the second lower source/drain pattern, and A semiconductor device in which the upper portion of the second lower contact is positioned at a vertical level higher than the upper portion of the first lower contact.
6. In Article 1, A semiconductor device in which the cross-sectional area of the second lower contact at a height corresponding to the bottom of the second lower source/drain pattern is larger than the cross-sectional area of the first lower contact at a height corresponding to the bottom of the first lower source/drain pattern.
7. A first channel pattern stacked in a first direction on a first region and having a first width in a second direction intersecting the first direction - the first channel pattern includes a first lower channel pattern and a first upper channel pattern spaced apart from the first lower channel pattern in the first direction -; A second channel pattern stacked in the first direction on a second region and having a second width greater than the first width in the second direction - the second channel pattern includes a second lower channel pattern and a second upper channel pattern spaced apart from the second lower channel pattern in the first direction -; A first gate electrode surrounding the first channel pattern and a second gate electrode surrounding the second channel pattern; A first lower source/drain pattern disposed on at least one side of the first lower channel pattern and a second lower source/drain pattern disposed on at least one side of the second lower channel pattern; A first lower contact penetrating the lower surface of the first lower source/drain pattern; and A second lower contact penetrating the lower surface of the second lower source/drain pattern above Includes, A semiconductor device in which the upper portion of the second lower contact is positioned at a vertical level higher than the upper portion of the first lower contact.
8. In Article 7, A semiconductor device in which the cross-sectional area of the second lower contact at a height corresponding to the bottom of the second lower source/drain pattern is larger than the cross-sectional area of the first lower contact at a height corresponding to the bottom of the first lower source/drain pattern.
9. In Article 7, Based on the third direction above, the width of the second lower contact decreases as it moves away from the second lower source/drain pattern, and A semiconductor device comprising a section in which the width of the first lower contact increases as it moves away from the first lower source/drain pattern.
10. In Article 9, A semiconductor device in which the section in which the width of the first lower contact increases is an area adjacent to the first lower source/drain pattern.

Description

Semiconductor Device The present disclosure relates to a semiconductor device. Semiconductor devices are core components used to control or amplify electrical signals in electronic devices, and various types of semiconductor devices can be manufactured. For example, memory devices are primarily used to store and retrieve data, while non-memory devices are used to control or amplify electrical signals. As key elements of electronic devices, semiconductor devices play an important role in diverse fields, such as computers, communication equipment, and consumer electronics. Semiconductor devices include integrated circuits composed of multiple transistors. As the size and design rules of semiconductor devices gradually shrink, the scale-down of transistors is also accelerating. As the size of transistors is reduced, the operating characteristics of the semiconductor device may degrade. Accordingly, various methods are being researched to form semiconductor devices with superior performance while overcoming the limitations associated with high integration of semiconductor devices. FIG. 1 is a layout diagram illustrating a first region of a semiconductor device according to some embodiments of the present disclosure. FIG. 2 is a layout diagram illustrating a second region of a semiconductor device according to some embodiments of the present disclosure. Figure 3 is a cross-sectional view taken along the line A-A' of Figure 1. Figure 4 is a cross-sectional view taken along the line B-B' of Figure 1. Figure 5 is a cross-sectional view taken along the line C-C' of Figure 2. Figure 6 is a cross-sectional view taken along the line D-D' of Figure 2. Figure 7 is an enlarged view of the X area of Figure 3. Figure 8 is an enlarged view of the Y region of Figure 5. FIGS. 9 to 11 are intermediate step drawings of a method for manufacturing a first region of a semiconductor device of the present disclosure. FIGS. 12 to 14 are intermediate step drawings of a method for manufacturing a second region of a semiconductor device of the present disclosure. A semiconductor device according to some embodiments of the present disclosure will be described in detail below with reference to the drawings. FIG. 1 is a layout diagram illustrating a first region of a semiconductor device according to some embodiment of the present disclosure. FIG. 2 is a layout diagram illustrating a second region of a semiconductor device according to some embodiment of the present disclosure. For convenience of explanation, only the first active pattern (AP1), the first gate electrode (120), the first lower source/drain pattern (151, 152), and the first lower contact (171, 172) are shown in FIG. 1, and only the second active pattern (AP2), the second gate electrode (220), the second lower source/drain pattern (251, 252), and the second lower contact (271, 272) are shown in FIG. 2. Referring to FIGS. 1 and 2, a semiconductor device according to some embodiments of the present disclosure may include a first region (R1) and a second region (R2). The first region (R1) and the second region (R2) may be spaced apart from each other. The first region (R1) and the second region (R2) may constitute different cells. For example, the first region (R1) may be a region constituting a Static Random Access Memory (SRAM), and the second region (R2) may be a region constituting a logic cell. However, not limited thereto, various semiconductor devices may be formed. A semiconductor device according to some embodiments may include a transistor, and more specifically, may include a three-dimensional multi-stack semiconductor device referred to as a gate-all-around (GAA) transistor or a multi-bridge channel FET (MBCFET). However, the present disclosure is not limited thereto. For example, the semiconductor device may include a fin-type transistor (FinFET) comprising a channel region having a fin-shaped pattern. The first active pattern (AP1) may include a first channel pattern (CP1). The first channel pattern (CP1) may be stacked in a first direction (D1). The second active pattern (AP2) may include a second channel pattern (CP2). The second channel pattern (CP2) may be stacked in a first direction (D1). A first active pattern (AP1) may be spaced apart from an adjacent first active pattern (AP1) in a second direction (D2). A second active pattern (AP2) may be spaced apart from an adjacent second active pattern (AP2) in a second direction (D2). Here, the second direction (D2) may be a direction that intersects (e.g., perpendicularly) with the first direction (D1). The first active pattern (AP1) and the second active pattern (AP2) may each extend into a third direction (D3) that intersects (e.g., perpendicularly) with the first direction (D1) and the second direction (D2), respectively. The first active pattern (AP1) may have a first width (W1) in the second direction (D2). The second active pattern (AP2) may have a second width (W2) in the second direction (D2). The first widt