KR-20260066945-A - SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THE SAME

Abstract

An exemplary embodiment of the present invention provides a semiconductor device comprising: a first semiconductor structure comprising a first semiconductor substrate and a first wiring layer disposed on the first semiconductor substrate and including first wiring structures and first bonding pads connected to the first wiring structures and exposed on the upper surface; a second semiconductor structure comprising a second semiconductor substrate disposed on the first semiconductor structure and a second wiring layer disposed on the lower surface of the second semiconductor substrate and including second wiring structures and second bonding pads connected to the second wiring structures and exposed on the lower surface; and a buffer structure extending from at least one side of the first semiconductor structure and the second semiconductor structure to a bonding surface between the first wiring layer and the second wiring layer.

Inventors

• 손성민
• 장주희
• 민준홍
• 이승돈
• 이현진
• 이호진

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260512

Application Date

20241105

Claims (10)

1. A first semiconductor structure comprising a first semiconductor substrate and a first wiring layer disposed on the first semiconductor substrate, the first wiring structures and first bonding pads connected to the first wiring structures and exposed on the upper surface; A second semiconductor structure comprising a second semiconductor substrate disposed on the first semiconductor structure and a second wiring layer disposed on the lower portion of the second semiconductor substrate, the second wiring structures being connected to the second wiring structures and including second bonding pads exposed on the lower surface; and A buffer structure extending from at least one side of the first semiconductor structure and the second semiconductor structure to the bonding surface between the first wiring layer and the second wiring layer. A semiconductor device including
2. In Article 1, The first bonding pads and the second bonding pads are joined together to form bonding structures, and the buffer structure extends from at least one side of the first semiconductor structure and the second semiconductor structure toward the outermost bonding structure among the bonding structures. A semiconductor device in which the upper surface of the buffer structure contacts the upper surface of the first semiconductor structure, the lower surface of the buffer structure contacts the lower surface of the second semiconductor structure, and the inner surface between the upper surface and the lower surface of the buffer structure contacts the outermost bonding structure.
3. In Article 1, The above buffer structure is, A first buffer layer having an outer surface extending from an inner surface and positioned inwardly to at least one side of the first semiconductor structure and the second semiconductor structure; and A semiconductor device comprising a second buffer layer having an inner surface in contact with the outer surface of the first buffer layer and an outer surface that forms a co-plane with at least one side of the first semiconductor structure and the second semiconductor structure.
4. In Paragraph 3, A semiconductor device having a first buffer layer having a first density and a second buffer layer having a second density greater than the first density.
5. In Article 1, The above buffer structure is a semiconductor device extending from at least two sides of the semiconductor device.
6. A first semiconductor substrate and a first semiconductor structure comprising a first wiring layer disposed on the first semiconductor substrate and including a first wiring structure; A second semiconductor substrate disposed on the first semiconductor structure and a second semiconductor structure disposed on the lower portion of the second semiconductor substrate and comprising a second wiring layer including a second wiring structure; Bonding structures formed by joining, in an upper and lower manner, first bonding pads connected to the first wiring structure and having an upper surface exposed from the first wiring layer, and second bonding pads connected to the second wiring structure and having a lower surface exposed from the second wiring layer; and A cushioning structure that fills a side depression recessed from the outside toward the outermost bonding structure among the bonding structures, between the upper surface of the first wiring layer and the lower surface of the second wiring layer. A semiconductor device including
7. A step of placing a first semiconductor wafer of a first thickness, comprising a first semiconductor substrate and a first wiring layer, on a carrier substrate; A step of forming a bonded structure by attaching a second semiconductor wafer of a second thickness onto the first semiconductor wafer; A step of injecting a first filler into a first depression formed at the edge of the bonding surface between the first semiconductor wafer and the second semiconductor wafer of the bonded structure; A step of injecting a second filler into a second depression on a first depression on the side of the first semiconductor wafer and the second semiconductor wafer of the bonded structure; A step of forming a buffer structure that buries the first and second depressions by hardening the first and second fillers; A step of thinning the back surface of the second semiconductor wafer to form a thickness smaller than the second thickness; A step of thinning the back surface of the first semiconductor wafer to form a thickness smaller than the first thickness; and Step of cutting the above bonded structure into unit chip structures A method for manufacturing a semiconductor device including
8. In Paragraph 7, The step of injecting the first filler is a method for manufacturing a semiconductor device in which a liquid insulating material having a first viscosity is injected into the first depression.
9. In paragraph 8, The step of injecting the second filler is a method for manufacturing a semiconductor device in which a liquid insulating material having a second viscosity higher than the first viscosity is injected into the second depression.
10. In Paragraph 9, A method for manufacturing a semiconductor device in which the step of curing the first filler and the second filler is such that impurities in the first filler vaporize and the filler is cured to have a first density.

Description

Semiconductor Device and Manufacturing Method of the Same The present invention relates to a semiconductor device and a method for manufacturing the same. With the increasing lightness and performance of electronic devices, there is a demand for the development of miniaturized and high-performance semiconductor chips. Although high performance can be achieved through the stacking structure of semiconductor chips, the process of attaching multiple semiconductor chips formed on a semiconductor wafer after dicing is carried out individually, resulting in a decrease in process yield. FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. FIGS. 2a to 9 are a perspective view, a cross-sectional view, and a top view illustrating each step of the manufacturing method of FIG. 1. FIGS. 10a to 10d are top views of a semiconductor device according to an exemplary embodiment. FIGS. 10e to 14 are cross-sectional views of a semiconductor device according to an exemplary embodiment. FIG. 15 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings. Unless otherwise specifically stated, terms such as 'upper,' 'upper surface,' 'lower,' 'lower surface,' and 'side surface' in this specification are based on the drawings and may actually vary depending on the direction in which the components are arranged. Additionally, ordinal numbers such as "first," "second," "third," etc., may be used as labels for specific elements, steps, directions, etc., to distinguish various elements, steps, directions, etc. from one another. Terms not described in the specification using "first," "second," etc., may still be referred to as "first" or "second" in the claims. Furthermore, terms referenced by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or another claim). In an embodiment, a first semiconductor wafer (100) having first chip regions (102) and a second semiconductor wafer (200) having second chip regions (202) are each formed, and the first semiconductor wafer (100) and the second semiconductor wafer (200) are bonded to form a bonded wafer structure. In an embodiment, semiconductor devices in which the first chip structure and the second chip structure are bonded can be formed by structurally reinforcing the bonded wafer structure, performing thinning, and then cutting into each bonded unit chip structure. FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment, and FIGS. 2a to 9 are a perspective view, a cross-sectional view, and a top view illustrating each step of the manufacturing method of FIG. 1. FIG. 2a is a perspective view illustrating two semiconductor wafers, and FIGS. 2b to 9 are cross-sectional views of the two semiconductor wafers cut along I-I', respectively. Referring to FIGS. 1, FIGS. 2a and FIGS. 2b, first chip regions (102) are formed on a first semiconductor wafer (100), second chip regions (202) are formed on a second semiconductor wafer (200), and the second semiconductor wafer (200) can be placed on the first semiconductor wafer (100) (S10). As shown in FIGS. 2a and 2b, a first semiconductor wafer (100) including a front surface (S1) and a rear surface (S2) can be placed on a base substrate (20), and first chip regions (102) can be formed on the front surface (S1). The first semiconductor wafer (100) includes a front surface (S1) and a rear surface (S2) opposite to the front surface (S1), and may include a first side surface (Sa) between the front surface (S1) and the rear surface (S2). The first side surface (Sa) of the first semiconductor wafer (100) may have a convex curved surface that protrudes outward from the edge of the front surface (S1) and the edge of the rear surface (S2). The first side surface (Sa) of the first semiconductor wafer (100) may have a curved surface overall, and may include a curved surface having an inflection point at the center of the first side surface (Sa) to have the largest diameter at the center of the first side surface (Sa), but is not limited thereto. First chip regions (102) may be arranged in a matrix form on the front surface (S1) of the first semiconductor wafer (100), and spacing regions (104) may be disposed between the first chip regions (102). The spacing regions (104) are spaces capable of separating the first chip regions (102) and may be defined as scribe lanes. The first chip regions (102) may occupy most of the area on the front surface (S1) of the first semiconductor wafer (100) and may be disposed in the area excluding the edge regions (E1a). Accordingly, the first semiconductor wafer (100) may include a first region (E1) corresponding to the front surface (S1) and a