KR-20260066958-A - MEMORY SYSTEM AND OPRATION METHOD FOR THE SAME

Abstract

The present invention relates to a memory system that efficiently supports a Flexible Data Placement (FDP) function and a method of operation of the memory system, comprising a memory device including a plurality of memory blocks and a controller that manages the plurality of memory blocks into N block groups, wherein the controller comprises N operation cores that manage access to each of the N block groups by mapping N physical address ranges corresponding to each of the N block groups to N first logical address ranges, and a control core that manages access to each of the N operation cores by dividing a second logical address range shared with a host into N sequential third logical address ranges and dynamically mapping each of the N third logical address ranges to each of the N first logical address ranges.

Inventors

• 이덕주
• 김동욱
• 권민철
• 장대훈

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260512

Application Date

20241105

Claims (20)

1. A memory device comprising a plurality of memory blocks; and It includes a controller that manages the above plurality of memory blocks into N block groups, and The above controller is, N operation cores that manage access to each of the N block groups by mapping N physical address ranges corresponding to each of the N block groups to N first logical address ranges; and A memory system comprising a control core that manages access to each of the N operation cores by dynamically mapping each of the N third logical address ranges and a second logical address range shared with a host into N sequential third logical address ranges, wherein N is a natural number greater than or equal to 2.
2. In paragraph 1, The above controller is, A memory system further comprising an internal memory for storing N first mapping tables corresponding to each of the N operation cores and a second mapping table corresponding to the control core.
3. In paragraph 2, Each of the above N operating cores is, A memory system that maps a corresponding physical address range among the N physical address ranges and a corresponding first logical address range among the N first logical address ranges, and manages the mapping in a corresponding first mapping table among the N first mapping tables.
4. In paragraph 3, Each of the above N operating cores is, A memory system that controls at least one of a background operation and a journaling operation within a corresponding block group among the N block groups by referring to a corresponding first mapping table among the N first mapping tables.
5. In paragraph 4, Each of the above N operation cores accumulates the operation state for each of the corresponding N block groups to generate N state information, and The above control core checks the N state information at set intervals and, according to the check result, dynamically maps each of the N third logical address ranges and each of the N first logical address ranges to a memory system managed in the second mapping table.
6. In paragraph 5, A memory system in which each of the above N operating cores accumulates the error rate occurring during the access operation for each of the corresponding N block groups as the operating state for each of the N block groups to generate the N state information.
7. In paragraph 5, A memory system in which each of the above N operation cores accumulates the type and number of background operations performed in each of the corresponding N block groups as an operation state for each of the N block groups to generate the N state information.
8. In paragraph 1, The above memory device is, It further includes a plurality of planes, each corresponding to a plurality of ways capable of inputting/outputting data in an interleaving manner by sharing a single channel, and each including the plurality of memory blocks. A memory system further comprising a plurality of memory dies, each corresponding to a plurality of channels capable of inputting/outputting data in an interleaving manner and each including a plurality of planes.
9. In paragraph 8, The above controller is, A memory system that groups any one memory block included in a first plane of any one of the plurality of memory dies and any one memory block included in a second plane into a single super memory block, and manages each of the N block groups by including at least one super memory block.
10. In paragraph 8, The above controller is, Any one memory block included in the first plane of the first memory die among the plurality of memory dies and any one memory block included in the first plane of the second memory die are grouped into a single super memory block, and Any single memory block included in the second plane of the first memory die and any single memory block included in the second plane of the second memory die are grouped into a single super memory block, A memory system that manages each of the above N block groups by including at least one super memory block.
11. In paragraph 8, The above controller is, A memory system that groups any one memory block included in the first plane of a first memory die among the plurality of memory dies, any one memory block included in the second plane of the first memory die, any one memory block included in the first plane of a second memory die, and any one memory block included in the second plane of the second memory die into one super memory block, and manages at least one super memory block in each of the N block groups.
12. A method of operation of a memory system comprising a memory device including a plurality of memory blocks, and a controller that manages the plurality of memory blocks into N block groups and includes a control core corresponding to a host and N operation cores corresponding to each of the N block groups, wherein A step of managing access to each of the N block groups by utilizing N first mapping tables, each containing information mapping between N physical address ranges and N first logical address ranges corresponding to each of the N block groups, in each of the N operation cores; A step of managing a second logical address range shared with the host in the control core by dividing it into N sequential third logical address ranges, A step of managing access to each of the N operation cores by using a second mapping table in the control core that includes information for dynamically mapping the N third logical address ranges and the N first logical address ranges, respectively. A method of operation of a memory system including, where N is a natural number greater than or equal to 2.
13. In Paragraph 12, A method of operation of a memory system further comprising the step of controlling at least one of a background operation and a journaling operation within a corresponding block group among the N block groups by referring to a corresponding first mapping table among the N first mapping tables in each of the N operation cores.
14. In Paragraph 13, A step of generating N state information by accumulating the operation state for each of the N block groups corresponding to each of the N operation cores; and A method of operation of a memory system further comprising the step of checking the N state information at each period set in the control core, and dynamically mapping each of the N third logical address ranges and each of the N first logical address ranges according to the result of the check and managing them in the second mapping table.
15. In Paragraph 14, A method of operation of a memory system further comprising the step of generating N state information by accumulating the error rate occurring during an access operation for each of the N block groups corresponding to each of the N operating cores as an operating state for each of the N block groups.
16. In Paragraph 14, A method of operation of a memory system further comprising the step of generating N state information by accumulating the types and number of background operations performed in each of the N block groups corresponding to each of the N operation cores as operation states for each of the N block groups.
17. In Paragraph 12, A method of operation of a memory system further comprising a plurality of planes, each corresponding to a plurality of ways capable of inputting/outputting data in an interleaving manner by sharing a single channel and each comprising the plurality of memory blocks, and a plurality of memory dies, each corresponding to a plurality of channels capable of inputting/outputting data in an interleaving manner and each comprising the plurality of planes.
18. In Paragraph 17, A method of operating a memory system further comprising the step of grouping any one memory block included in a first plane of any one of the plurality of memory dies and any one memory block included in a second plane into a single super memory block, and managing at least one super memory block in each of the N block groups.
19. In Paragraph 17, A method of operating a memory system further comprising the step of grouping any one memory block included in the first plane of a first memory die among the plurality of memory dies and any one memory block included in the first plane of a second memory die into one super memory block, grouping any one memory block included in the second plane of the first memory die and any one memory block included in the second plane of the second memory die into one super memory block, and managing at least one super memory block in each of the N block groups.
20. In Paragraph 17, A method of operating a memory system further comprising the step of grouping any one memory block included in the first plane of a first memory die among the plurality of memory dies, any one memory block included in the second plane of the first memory die, any one memory block included in the first plane of a second memory die, and any one memory block included in the second plane of the second memory die into one super memory block, and managing at least one super memory block in each of the N block groups.

Description

Memory System and Operation Method for the Same The present invention relates to a memory system, and more specifically, to a memory system that efficiently supports a Flexible Data Placement (FDP) function and a method of operating the memory system. Recently, the paradigm of the computing environment is shifting toward ubiquitous computing, which enables the use of computer systems anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and laptop computers is surging. These portable electronic devices generally utilize memory systems that employ memory devices—in other words, data storage devices. Data storage devices are used as the primary or secondary memory of portable electronic devices. Data storage devices utilizing non-volatile memory, unlike hard disks, lack mechanical moving parts, offering superior stability and durability. Additionally, they have the advantages of very fast information access speeds and low power consumption. Examples of memory systems possessing these advantages include USB (Universal Serial Bus) memory devices, memory cards with various interfaces, and Solid State Drives (SSDs). Meanwhile, users of memory systems want to store as much data efficiently and flexibly as they need and arrange that data in a specific manner through the Flexible Data Placement (FDP) function. However, supporting the FDP function in a memory system requires managing the storage space by partitioning it across multiple cores; this can increase the size of mapping information and cause rebuild times to increase in the event of errors. FIGS. 1a and FIGS. 1b are drawings for illustrating an example of a data processing system including a memory system according to an embodiment of the present invention. FIG. 2 is a diagram illustrating the concept of a block group used in a memory system according to an embodiment of the present invention. FIGS. 3a to 3c are drawings for explaining an example of an operation to control a plurality of storage spaces through a multi-stage mapping operation in a memory system according to an embodiment of the present invention. FIGS. 4a to 4c are drawings for explaining other examples of operations for controlling a plurality of storage spaces through a multi-stage mapping operation in a memory system according to an embodiment of the present invention. Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below and may be configured in various different forms; the embodiments provided are merely intended to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the present invention. FIGS. 1a and FIGS. 1b are drawings for illustrating an example of a data processing system including a memory system according to an embodiment of the present invention. Referring to FIG. 1a and FIG. 1b, another data processing system in an embodiment of the present invention may include a host (102) and a memory system (110). The memory system (110) may include a memory device (150) and a controller (130). The memory system (110) may be a device that stores data under the control of a host (102), such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system. The memory device (150) and the controller (130) included in the memory system (110) may be physically distinct components. Additionally, the memory device (150) and the controller (130) may be functionally distinct components. Furthermore, the memory device (150) and the controller (130) may be connected by at least one data path. For example, the data path may consist of channels and/or ways. Additionally, the memory device (150) and the controller (130) may be implemented through a single semiconductor device chip or multiple semiconductor device chips. Furthermore, in the case of a memory system (110) requiring high integration density, the memory device (150) and the controller (130) may be composed of a single semiconductor device chip. The memory system (110) can be manufactured as any one of various types of storage devices according to the host interface, which is the method of communication with the host (102). For example, the memory system (110) can be configured as any one of various types of storage devices such as an SSD, MMC, eMMC, RS-MMC, micro-MMC type multimedia card, SD, mini-SD, micro-SD type secure digital card, USB (universal serial bus) storage device, UFS (universal flash storage) device, PCMCIA (personal computer memory card international association) card type storage device, PCI (peripheral component interconnection) card type storage device, PCI-E (PCI express) card type storage device, CF (compact flash) card, smart media card, memory stick, etc. The memory sys