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KR-20260067002-A - BUFFER FOR INTERPOLATION FUNCTION

KR20260067002AKR 20260067002 AKR20260067002 AKR 20260067002AKR-20260067002-A

Abstract

A buffer having an interpolation function according to an embodiment of the present invention comprises: a first circuit composed of a plurality of transistors for receiving a first input voltage and a second input voltage; an output unit for outputting an interpolated voltage between the first input voltage and the second input voltage; a second circuit composed of a plurality of transistors for expanding the range of the first input voltage or the second input voltage; and a plurality of switches for removing standby current of the buffer.

Inventors

  • 신승화
  • 김현식
  • 신경민
  • 안용성

Assignees

  • 주식회사 엘엑스세미콘
  • 한국과학기술원

Dates

Publication Date
20260512
Application Date
20241105

Claims (6)

  1. In a buffer equipped with an interpolation function, A first circuit composed of a plurality of transistors receiving a first input voltage and a second input voltage; An output unit that outputs an interpolated voltage between the first input voltage and the second input voltage; A second circuit composed of a plurality of transistors for expanding the range of the first input voltage or the second input voltage; and Multiple switches for removing standby current of the above buffer A buffer equipped with an interpolation function including
  2. In paragraph 1, The above first circuit is, It includes at least four transistors, The voltage applied to the gate and source of the first transistor and the voltage applied to the gate and source of the second transistor are the same, A buffer having an interpolation function characterized in that the voltage applied to the gate and source of the third transistor and the voltage applied to the gate and source of the fourth transistor are the same.
  3. In paragraph 2, A first current source that applies a first external current to the third transistor; and A second current source that applies a second external current to the fourth transistor. A buffer equipped with an interpolation function that further includes
  4. In paragraph 3, The first external current of the first current source is applied to the fourth transistor, and A first switch that applies the second external current of the second current source to the third transistor. A buffer equipped with an interpolation function that further includes
  5. In paragraph 4, The above plurality of switches are, When the above second input voltage is high, it is turned off, and A buffer having an interpolation function, characterized by including a second switch and a third switch that are turned on when the second input voltage is low.
  6. In paragraph 5, The above second circuit is, Three transistors connected in series and in parallel with the second switch mentioned above, and A buffer having an interpolation function, characterized by including three transistors connected in series and connected in parallel with the third switch.

Description

Buffer for Interpolation Function The present invention is directly or indirectly related to a buffer equipped with an interpolation function. For example, it can be applied to high-speed amplifier circuits capable of voltage interpolation (True-DC-Interpolative Super-OTA Buffer Amplifier). Recently, as the metaverse has gained prominence as a next-generation IT technology, interest in the development of AR (Augmented Reality) and VR (Virtual Reality) related devices to realize an immersive metaverse is increasing explosively. Since AR/VR related devices require portability and high resolution (PPI, Pixels Per Inch), there have recently been attempts to apply OLEDoS (OLED on Silicon) as a display technology to AR/VR related devices. In OLEDoS, the miniaturization of resolution (PPI) requires not only OLED process technology but also ultra-low-area column-driver channel circuit design technology in CMOS (Complementary Metal Oxide Semiconductor) driver ICs that matches a very small pixel pitch. Furthermore, to realize a smoother UX (User Experience)/UI (User Interface), high-speed driving technology of 144Hz or higher, surpassing the conventional 90Hz refresh rate limit, is required. Additionally, the color depth of existing OLEDoS is very low at the 4-bit level, requiring improvement to 10-bit or higher, comparable to TVs. FIG. 1 illustrates a buffer equipped with an interpolation function according to the prior art. FIG. 2 is a block diagram of a buffer having an interpolation function according to an embodiment of the present invention. FIG. 3 is an example of a circuit diagram of a buffer having an interpolation function according to an embodiment of the present invention. Figure 4 illustrates the voltage change of the translinear loop in the circuit diagram of Figure 3. FIG. 5 is another example of a circuit diagram of a buffer having an interpolation function according to an embodiment of the present invention. Figure 6 is a graph showing the relationship between the input voltage and output voltage of Figures 3 and 5. FIG. 7 illustrates the operation of a plurality of switches shown in FIG. 5. FIG. 8 is a graph showing the relationship between the input voltage and the quiescent current for cases where the multiple switches shown in FIG. 5 are present and cases where they are not. Figure 9 illustrates the case where a rising step input voltage is applied. Figure 10 shows the changes in voltage and current over time of the circuit illustrated in Figure 9. FIG. 11 is a graph showing the result of a high SR (Slew Rate) according to an embodiment of the present invention. FIG. 12 illustrates a buffer including both an N-type DIP (Differential Input Pair) and a P-type PIP according to an embodiment of the present invention. Also, FIG. 13 illustrates in detail the N-type DIP and P-type DIP shown in FIG. 12. The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Throughout the specification, identical reference numbers denote substantially identical components. In the following description, detailed descriptions of components and functions known in the art may be omitted if they are not related to the core components of the present invention. Where terms such as 'comprising,' 'having,' 'consisting of,' etc. are used in this specification, other parts may be added unless 'only' is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise. In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement. Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention. The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of the first item, the second item, and the third item” may mean not only the first item, the second item, or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item. The features of each of the various embodiments of the present inventio